scholarly journals Single-Event Upsets in Microelectronics

MRS Bulletin ◽  
2003 ◽  
Vol 28 (2) ◽  
pp. 107-110 ◽  
Author(s):  
Henry H.K. Tang ◽  
Nils Olsson

AbstractThis article introduces the February 2003 issue of MRS Bulletin on “Single-Event Upsets (SEUs) in Microelectronics.” These radiation effects in devices and circuits have been recognized in recent years as a key reliability concern for many current and future silicon-based technologies. This introduction sets the scope for critical discussions on this subject. The articles in the issue reflect the interdisciplinary nature of SEU research. The contributing authors include experts from several specializations: technology reliability, materials science, device physics, circuit designs, and theoretical and experimental nuclear physics. We review the current understanding of SEU problems from the perspectives of radiation physics, circuit design issues, and global technology developments. The discussions cover the key areas of modeling, circuit analyses, accelerator tests and experiments, basic nuclear data, and environmental neutron measurements.

MRS Bulletin ◽  
2003 ◽  
Vol 28 (2) ◽  
pp. 121-125 ◽  
Author(s):  
Jan Blomgren ◽  
Bo Granbom ◽  
Thomas Granlund ◽  
Nils Olsson

AbstractThis article approaches single-event upset (SEU) problems from the standpoint of experimental nuclear physics, with a focus on certain neutron experiments and neutron data essential for SEU studies. A review is given of some research programs, both basic and applied, that are strongly motivated by SEU applications. Some specific examples are presented from the The (short for Theodor) Svedberg Laboratory (TSL) in Uppsala, Sweden: First, using the quasi-monoenergetic neutron beam, SEU cross sections (of chips) are measured over the neutron energy range of 20–150 MeV. Data from the same technology generation, in general, can be fitted into a simple curve. Second, the particle origins of SEUs are discussed from the framework of neutron–nucleus spallation reactions.


2011 ◽  
Vol 110-116 ◽  
pp. 4505-4511
Author(s):  
M. Mager ◽  
L. Musa ◽  
A. Rehman ◽  
A. Szczepankiewicz

The Time Projection Chamber of the ALICE ex- periment at the CERN Large Hadron Collider features highly integrated on-detector read-out electronics. It is following the general trend of high energy physics experiments by placing the front-end electronics as close to the detector as possible—only some 10 cm away from its active volume. Being located close to the beams and the interaction region, the electronics is subject to a moderate radiation load, which allowed us to use commercial off-the-shelf components. However, they needed to be selected and qualified carefully for radiation hardness and means had to be taken to protect their functionality against soft errors, i. e. single event upsets. Here we report on the first measurements of LHC induced radiation effects on ALICE front-end electronics and on how they attest to expectations.


2020 ◽  
Vol 70 (3) ◽  
pp. 272-277
Author(s):  
Balasubramanian P. ◽  
S. Moorthi

Due to the advances in electronics design automation industry, worldwide, the integrated approach to model and emulate the single event effects due to cosmic radiation, in particular single event upsets or single event transients is gaining momentum. As of now, no integrated methodology to inject the fault in parallel to functional test vectors or to estimate the effects of radiation for a selected function in system on chip at design phase exists. In this paper, a framework, PRogrammable single Event effects Demonstrator for dIgital Chip Technologies (PREDICT) failure assessment for radiation effects is developed using a hardware platform and aided by genetic algorithms addressing all the above challenges. A case study is carried out to evaluate the frameworks capability to emulate the effects of radiation using the co-processor as design under test (DUT) function. Using the ML605 and Virtex-6 evaluation board for single and three particle simulations with the layered atmospheric conditions, the proposed framework consumes approximately 100 min and 300 min, respectively; it consumes 600 min for 3 particle random atmospheric conditions, using the 64 GB RAM, 64-bit operating system with 3.1 GHz processor based workstation. The framework output transforms the 4 MeVcm2/mg linear energy transfer to a single event transient pulse width of 2 μs with 105 amplification factor for visualisation, which matches well with the existing experimental results data. Using the framework, the effects of radiation for the co-processing module are estimated during the design phase and the success rate of the DUT is found to be 48 per cent.


2002 ◽  
Author(s):  
C. H. Truong ◽  
E. J. Simburger ◽  
R. C. Lacoe ◽  
J. C. Ross ◽  
S. Brown

2021 ◽  
Vol 20 (3) ◽  
pp. 1-25
Author(s):  
James Marshall ◽  
Robert Gifford ◽  
Gedare Bloom ◽  
Gabriel Parmer ◽  
Rahul Simha

Increased access to space has led to an increase in the usage of commodity processors in radiation environments. These processors are vulnerable to transient faults such as single event upsets that may cause bit-flips in processor components. Caches in particular are vulnerable due to their relatively large area, yet are often omitted from fault injection testing because many processors do not provide direct access to cache contents and they are often not fully modeled by simulators. The performance benefits of caches make disabling them undesirable, and the presence of error correcting codes is insufficient to correct for increasingly common multiple bit upsets. This work explores building a program’s cache profile by collecting cache usage information at an instruction granularity via commonly available on-chip debugging interfaces. The profile provides a tighter bound than cache utilization for cache vulnerability estimates (50% for several benchmarks). This can be applied to reduce the number of fault injections required to characterize behavior by at least two-thirds for the benchmarks we examine. The profile enables future work in hardware fault injection for caches that avoids the biases of existing techniques.


2005 ◽  
Vol 52 (6) ◽  
pp. 2319-2325 ◽  
Author(s):  
J. Baggio ◽  
V. Ferlet-Cavrois ◽  
D. Lambert ◽  
P. Paillet ◽  
F. Wrobel ◽  
...  

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