Fundamentals of Slurry Design for CMP of Metal and Dielectric Materials

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 752-760 ◽  
Author(s):  
Rajiv K. Singh ◽  
Seung-Mahn Lee ◽  
Kyu-Se Choi ◽  
G. Bahar Basim ◽  
Wonseop Choi ◽  
...  

AbstractThe formulation of slurries for chemical–mechanical planarization (CMP) is currently considered more of an art than a science, due to the lack of understanding of the wafer, slurry, and pad interactions involved. Several factors, including the large number of input variables for slurries and the synergistic interplay among input variables and output parameters, further complicate our ability to understand CMP phenomena. This article provides a fundamental basis for the choice of chemical additives and particles needed for present-day and next-generation slurry design. The effect of these components on nanoscale and microscale interaction phenomena is investigated. Methodologies are suggested for the development of next-generation slurries required to overcome CMP challenges related to defectivity and the surface topography of soft materials such as Low-κ dielectrics and copper.

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.


Author(s):  
Christian Wendeln ◽  
Edith Steinhäuser ◽  
Lutz Stamp ◽  
Bexy Dosse-Gomez ◽  
Elisa Langhammer ◽  
...  

The deposition of electroless Copper on dielectric substrates and the subsequent electrolytic build-up of a thicker Copper layer are widely used steps within the production of modern Printed Circuit Boards (PCB), and while there have been numerous developments within PCB production, the current manufacturing technologies continue to be reliant on the autocatalytic deposition of Copper from a solution containing formaldehyde as the reducing agent, even though the chemistry is known to pose a risk to human health. Further, as the high volatility of formaldehyde generally increases the exposure to the hazard, it is understood that critical air concentrations can easily be exceeded. With this in mind it is clear that the development of environmental and user friendly electroless Copper baths has become a subject of importance. Nevertheless, the introduction of “green” plating chemistry into the market remains a challenge due to high industrial standards in terms of performance and cost-efficiency, which have been established by the conventional plating products and limit their replacement. In the case of the electroless Copper baths, formaldehyde-free alternatives have to show excellent substrate coverage with metal, provide coatings with high conductivity and uniformity and should lead to very good reliability results. Moreover, the solution, and final Copper layer have to function with the diverse range of dielectric materials that are currently employed. Due to application needs, there has been a shift within PCB design towards the use of very smooth substrate materials with low coefficients of thermal expansion. Such materials offer the opportunity for further miniaturization of circuits and are optimal for adoption within packaged die components (IC substrates). However, smooth substrate topographies typically lead to a limited adhesion of the electroless Copper layer, and increases the risk of delamination or blister formation. To prevent this, the properties of the metal film itself, as well as the chemical properties of the Copper bath, from which it is deposited, are critical, with a key factor being that the deposited layer is generated under internal tensile stress, as this has been shown to be of importance in reducing blister occurrence. While formaldehyde based plating solutions have been modified to satisfy this requirement through the adoption of additives and organic substances, there is still very little experience available regarding chemical approaches utilizing other reducing agents. Changing the reducing agent generally requires a complete redesign of the electroless system, including careful selection of the complexing agents and additives, readjustment of the chemical concentrations and optimization of the baths physical operating conditions. In this work we describe a new type of formaldehyde-free electroless Copper solution suitable for a broad set of applications and materials, and specifically the processing of next-generation substrates. This new plating solution has been successfully applied in both laboratory and production-scale environments, with its performance being evaluated and benchmarked against an existing formaldehyde-containing reference. The obtained metal layer has been characterized through a number of analytical techniques, including microscopy, XRF, SEM, adhesion tests as well as non-blister performance. Based on the data obtained we believe that the newly developed solution utilizing a non-formaldehyde reducing agent provides a suitable technology for PCB production without a loss of process performance, and thus provide a sustainable “green” alternative to the industry.


2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000986-001015
Author(s):  
Eric Huenger ◽  
Joe Lachowski ◽  
Greg Prokopowicz ◽  
Ray Thibault ◽  
Michael Gallagher ◽  
...  

As advanced packaging application space evolves and continues to deviate from the conventional shrinkage pathway predicted by Moore's law, material suppliers need to continue to work with OEMs, OSATs and Foundries to identify specific opportunities. One such opportunity continues to present itself in developing new materials to support new platforms for next generation products to support 3D chip stacking and TSV applications. The newer material sets can be established to meet more challenging design requirements associated with the demands, presented by the application from both a physical/lithographical processing and design perspective. Next generation packages requires the development of new dielectric materials that can support both the physical demands of 3D chip stacking and TSV package design aspects while maintaining strengths of the existing material platform. While vertical integration necessitates the use of thinned substrates and its associated integration challenges, there is a continuing need to support horizontal shrinkage typical of the Moore's Law, which pushes the lithography envelope requiring finer pitch and smaller feature resolution capability. This presentation identifies the strategy we have taken and highlights approach taking in the development of low temperature curable photoimageable dielectric materials with enhanced lithographic performance. We will discuss the methodology used to create benzocyclobutene based dielectric material curable at 180 °C and show how lithographic performance can be tuned to allow sub 5 micron via using broad band illumination. Finally we will review the impact of low temperature processing on the mechanical, thermal and electrical properties of this novel photoimageable dielectric material.


2019 ◽  
Vol 7 (32) ◽  
pp. 9782-9802 ◽  
Author(s):  
Kootak Hong ◽  
Tae Hyung Lee ◽  
Jun Min Suh ◽  
Seok-Hyun Yoon ◽  
Ho Won Jang

This review highlights the critical issues and recent advances in developing highly volumetric-efficient and high capacitance MLCCs from the viewpoint of designing dielectric materials.


2008 ◽  
Vol 389-390 ◽  
pp. 498-503
Author(s):  
N. Qin ◽  
Dong Ming Guo ◽  
Ren Ke Kang ◽  
Feng Wei Huo

The calculating model of surface non-uniformity of polishing pad and the kinematical model between polishing pad and conditioner are initially established. Then the effects of several conditioning parameters were investigated by using the two models. The results of simulation and calculation show that the width ratio of diamond band of conditoner and the rotation speed at the same speed ratio between pad and conditioner have little effect on the surface non-uniformity of polishing pad, while at high non-integer rotation speed ratio, the surface non-uniformity of polishing pad is better than that at low integer speed ratio. The research results are available to select appropriate conditioning parameters especially for the stringent requirement of within-wafer non-uniformity in next generation IC.


2008 ◽  
Vol 53-54 ◽  
pp. 265-272
Author(s):  
Dong Ming Guo ◽  
N. Qin ◽  
Ren Ke Kang ◽  
Zhu Ji Jin

Among the properties of polishing pad, the surface roughness plays a crucial role in CMP (Chemical Mechanical Planarization) process. However, there is no acknowledged standard for measuring and characterizing the roughness of pad surface in 3D measurement. In this paper Talysurf CLI 2000 working on the principle of dynamic confocal measurement was initially suggested to measure the 3D surface topography of polishing pads through theoretical and experimental analysis. In addition, based on the Nyquist folding frequency and the statistical theory, a selection technique for sampling interval and sampling area was proposed and verified through experiments. The results showed that Talysurf CLI 2000 is more suitable than NewView to measure the 3D surface topography of polishing pads. 2μm sampling interval, 0.5×0.5mm2 sampling area and 10μm interval, 1×1mm2 area are respectively recommended for IC1000/SubaIV and SubaIV polishing pad.


2012 ◽  
Vol 455-456 ◽  
pp. 1145-1148
Author(s):  
Yan Gang He ◽  
Jia Xi Wang ◽  
Xiao Wei Gan ◽  
Wei Juan Li ◽  
Yu Ling Liu

With the microelectronic technology node moves down to 45 nm and beyond, and to reduce the RC delay time, low-k dielectric materials have been used to replace regular dielectric materials. Therefore, the down force of chemical mechanical planarization (CMP) needs to decrease based on the characteristics of low-k materials: low mechanical strength. In this study, the effect of new complex agent on copper dissolution in alkaline slurry for CMP was investigated. Based on the reaction mechanism analysis of Cu in alkaline slurry in CMP, the performance of Cu removal rate and surface roughness condition were discussed. It has been confirmed that Cu1 slurry demonstrates a relatively high removal rate with low down force. And also, by utilizing the Cu1 slurry, good result of Cu surface roughness were obtained.


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