Effects of Silicon Front Surface Topography on Silicon Oxide Chemical Mechanical Planarization

1999 ◽  
Vol 1 (4) ◽  
pp. 181 ◽  
Author(s):  
C. Shan Xu
Keyword(s):  
Surface Topography ◽  
Silicon Oxide ◽  
Chemical Mechanical Planarization ◽  
Front Surface

Advances in Chemical-Mechanical Planarization

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj
Keyword(s):  
Surface Topography ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Fundamental Understanding ◽  
Copper Polishing ◽  
Future Growth

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

Novel Measurement Technique on 3D Surface Topography of Polishing Pad

2008 ◽  
Vol 53-54 ◽  
pp. 265-272
Author(s):  
Dong Ming Guo ◽  
N. Qin ◽  
Ren Ke Kang ◽  
Zhu Ji Jin
Keyword(s):  
Surface Topography ◽  
Chemical Mechanical Planarization ◽  
Sampling Interval ◽  
3D Measurement ◽  
Sampling Area ◽  
Polishing Pad ◽  
3D Surface ◽  
3D Surface Topography ◽  
Planarization Process ◽  
Polishing Pads

Among the properties of polishing pad, the surface roughness plays a crucial role in CMP (Chemical Mechanical Planarization) process. However, there is no acknowledged standard for measuring and characterizing the roughness of pad surface in 3D measurement. In this paper Talysurf CLI 2000 working on the principle of dynamic confocal measurement was initially suggested to measure the 3D surface topography of polishing pads through theoretical and experimental analysis. In addition, based on the Nyquist folding frequency and the statistical theory, a selection technique for sampling interval and sampling area was proposed and verified through experiments. The results showed that Talysurf CLI 2000 is more suitable than NewView to measure the 3D surface topography of polishing pads. 2μm sampling interval, 0.5×0.5mm2 sampling area and 10μm interval, 1×1mm2 area are respectively recommended for IC1000/SubaIV and SubaIV polishing pad.

Chemical-Mechanical Planarization of Aluminum-Based Alloys for Multilevel Metallization

MRS Bulletin ◽  
1995 ◽  
Vol 20 (11) ◽  
pp. 61-64 ◽  
Author(s):  
M.A. Fury ◽  
D.L. Scherber ◽  
M.A. Stell
Keyword(s):  
Silicon Oxide ◽  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Small Diameter ◽  
Copper Metallization ◽  
Yield Data ◽  
Technical Community ◽  
Yield Learning ◽  
History Of ◽  
Process Strategy

As recently as 1993, the prevailing presumption among the semiconductor technical community was that then-current development efforts associated with aluminum lines and tungsten damascene vias needed to shift rapidly to copper multilevel interconnect schemes. This is exemplified by the June 1993 issue of the MRS Bulletin, which featured copper metallization as its theme. In the intervening years, however, that same technical community revised the Semiconductor Industry Association (SIA) roadmap and placed renewed emphasis on the use of an all-aluminum interconnect scheme. This was done largely in deference to the costs associated with converting existing semiconductor lines to copper-compatible facilities. In addition to tooling costs, there is a learning curve for copper systems that remains to be established for device reliability, field failures, yield learning, and process maturation. On the other hand, existing fabs are already compatible with aluminum metallurgies, and there is a rich history of reliability and yield data.This change in direction creates two immediate needs: (1) the need to fill small-diameter vertical interconnects (vias) with void-free aluminum and (2) the need to remove the top surface aluminum resulting from its blanket deposition (overburden) following the metal fill. In addition, for high circuit-density applications, it may be desirable, if not necessary, to form the metal lines using the same damascene fill method as is used for the vias. This process strategy replaces metal etching and insulator gap fill with insulator (usually silicon oxide) etching and metal gap fill.

Fundamentals of Slurry Design for CMP of Metal and Dielectric Materials

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 752-760 ◽  
Author(s):  
Rajiv K. Singh ◽  
Seung-Mahn Lee ◽  
Kyu-Se Choi ◽  
G. Bahar Basim ◽  
Wonseop Choi ◽  
...  
Keyword(s):  
Surface Topography ◽  
Chemical Mechanical Planarization ◽  
Soft Materials ◽  
Dielectric Materials ◽  
Next Generation ◽  
Chemical Additives ◽  
Input Variables ◽  
Interaction Phenomena

AbstractThe formulation of slurries for chemical–mechanical planarization (CMP) is currently considered more of an art than a science, due to the lack of understanding of the wafer, slurry, and pad interactions involved. Several factors, including the large number of input variables for slurries and the synergistic interplay among input variables and output parameters, further complicate our ability to understand CMP phenomena. This article provides a fundamental basis for the choice of chemical additives and particles needed for present-day and next-generation slurry design. The effect of these components on nanoscale and microscale interaction phenomena is investigated. Methodologies are suggested for the development of next-generation slurries required to overcome CMP challenges related to defectivity and the surface topography of soft materials such as Low-κ dielectrics and copper.

Effects of Properties and Growth Parameters of Doped and Undoped Silicon Oxide Films on Wear Behavior During Chemical Mechanical Planarization Process

2004 ◽  
Vol 19 (4) ◽  
pp. 996-1010 ◽  
Author(s):  
A.K. Sikder ◽  
Ashok Kumar ◽  
S. Thagella ◽  
Jiro Yota
Keyword(s):  
Silicon Oxide ◽  
Wear Behavior ◽  
Growth Parameters ◽  
Chemical Mechanical Planarization ◽  
Oxide Films ◽  
Chemical Vapor ◽  
Copper Metallization ◽  
Depth Sensing ◽  
Before And After ◽  
Planarization Process

Understanding the tribological, mechanical, and structural properties of an inorganic and organic dielectric layer in the chemical mechanical planarization (CMP) process is crucial for successful evaluation and implementation of these materials with copper metallization. Polishing behaviors of different carbon- and fluorine-doped silicon dioxide (SiO2) low dielectric constant materials in CMP process are discussed in this paper. Films were deposited using both chemical vapor deposition and spin-on method. Carbon and fluorine incorporation in the Si–O network weaken the mechanical integrity of the structure and behave differently in slurry selective to SiO2 films. Mechanical properties of the films were measured using depth-sensing nanoindentation technique, and it was found that undoped SiO2 film has the highest and spin-on carbon-doped oxide films have the lowest hardness and modulus values. Wear behavior of the doped SiO2 is studied in a typical SiO2 CMP environment, and results are analyzed and compared with those of the undoped SiO2 films. Coefficient of friction and acoustic emission signals have significant effect on the polishing behavior. Surface of the films are investigated before and after polishing using atomic force microscopy. Roughness and section analysis of the films after polishing show the variation in wear mechanism. Validation of Preston’s equation is discussed in this study. Additionally, different wear mechanisms are presented, and a two body abrasion model is proposed for the softer films.

scholarly journals Dynamic Pad Surface Metrology Monitoring by Swing-Arm Chromatic Confocal System

2020 ◽  
Vol 11 (1) ◽  
pp. 179
Author(s):  
Chao-Chang A. Chen ◽  
Jen-Chieh Li ◽  
Wei-Cheng Liao ◽  
Yong-Jie Ciou ◽  
Chun-Chen Chen
Keyword(s):  
Surface Topography ◽  
Removal Rate ◽  
Chemical Mechanical Planarization ◽  
Surface Profile ◽  
Performance Level ◽  
Wafer Surface ◽  
Surface Metrology ◽  
Effective Lifetime ◽  
Polishing Pad ◽  
Swing Arm

This study aims to develop a dynamic pad monitoring system (DPMS) for measuring the surface topography of polishing pad. Chemical mechanical planarization/polishing (CMP) is a vital process in semiconductor manufacturing. The process is applied to assure the substrate wafer or thin film on wafer that has reached the required planarization after deposition for lithographic processing of the desired structures of devices. Surface properties of polishing pad have a huge influence on the material removal rate (MRR) and quality of wafer surface by CMP process. A DPMS has been developed to analyze the performance level of polishing pad for CMP. A chromatic confocal sensor is attached on a designed fixture arm to acquire pad topography data. By swing-arm motion with continuous data acquisition, the surface topography information of pad can be gathered dynamically. Measuring data are analyzed with a designed FFT filter to remove mechanical vibration and disturbance. Then the pad surface profile and groove depth can be calculated, which the pad’s index PU (pad uniformity) and PELI (pad effective lifetime index) are developed to evaluate the pad’s performance level. Finally, 50 rounds of CMP experiments have been executed to investigate the correlations of MRR and surface roughness of as-CMP wafer with pad performance. Results of this study can be used to monitor the pad dressing process and CMP parameter evaluation for production of IC devices.

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