Bias Temperature Instability (BTI) in high-mobility channel devices with high-k dielectric stacks: SiGe, Ge, and InGaAs

MRS Advances ◽  
2016 ◽  
Vol 1 (49) ◽  
pp. 3329-3340 ◽  
Author(s):  
J. Franco ◽  
B. Kaczer ◽  
A. Vais ◽  
A. Alian ◽  
H. Arimura ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
High Mobility ◽  
Time Dependent ◽  
Gate Stack ◽  
Model Framework ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
High K ◽  
Material Systems ◽  
High Mobility Channel

ABSTRACTWe present a review of our recent studies of Bias Temperature Instability (BTI) in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) fabricated with different material systems, highlighting the reliability opportunities and challenges of each novel device family. We discuss first the intrinsic reliability improvement offered by SiGe and Gep-channel technologies, if a Si cap is used to passivate the channel, in order to fabricate a standard SiO2/HfO2gate stack. We focus on SiGe gate stack optimizations for maximum BTI reliability, and on a simple physics-based model able to reproduce the experimental trends. This model framework is then used to understand the suboptimal BTI reliability and excessive time-dependent variability induced by oxide defect charging in different high-mobility channel gate stacks, such as Ge/GeOx/high-k and InGaAs/high-k. Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability and minimize time-dependent variability.

Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling

MRS Advances ◽  
2017 ◽  
Vol 2 (52) ◽  
pp. 2973-2982 ◽  
Author(s):  
Andreas Kerber
Keyword(s):  
Dielectric Breakdown ◽  
Cmos Technology ◽  
Gate Stack ◽  
Leakage Currents ◽  
Technology Scaling ◽  
Device Scaling ◽  
Novel Device ◽  
Time Dependent Dielectric Breakdown ◽  
Bias Temperature Instability ◽  
High K

ABSTRACTMG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.

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