Electrostatic Microelectromechanical Logic Devices Made by CMOS-compatible Surface Micromachining

2020 ◽  
Vol 140 (1) ◽  
pp. 2-13
Author(s):  
Makoto Mita ◽  
Manabu Ataka ◽  
Hiroshi Toshiyoshi
Keyword(s):  
Surface Micromachining ◽  
Logic Devices ◽  
Cmos Compatible

A Bistable Electromagnetic Actuated Microvalve With Integrated Switching Mechanism

Materials ◽  
2003 ◽  
Author(s):  
Jemmy Sutano Bintoro ◽  
Peter J. Hesketh
Keyword(s):  
Fabrication Method ◽  
Surface Micromachining ◽  
Switching Mechanism ◽  
Valve Structure ◽  
Closed Position ◽  
Cmos Compatible

This paper presents a new design and fabrication method for a bistable electromagnetic actuated microvalve. The complete magnetically close structure has been designed by ANSYS 5.7 [1] and was fabricated in 7 masks steps. The fabrication processes were entirely done by surface micromachining and electroplating on a single wafer with the maximum fabrication temperature of 300 °C, providing potentially a CMOS compatible process. The microvalve has additional feature called integrated switching mechanism used to detect the position of the membrane under fully open or closed position. The fabrication steps for the microvalve are different from previous work; the hole is etched through the back of wafer after the whole valve structure been built on the top of wafer. This provides the flexibility to fabricate an actuator first before finally producing a microvalve.

A Structure of Bistable Electromagnetic Actuated Microvalve Fabricated on a Single Wafer, Implementing the SLA and PDMS Technique

2003 ◽  
Author(s):  
Jemmy Sutanto Bintoro ◽  
Rajesh Luharuka ◽  
Edward W. Wong ◽  
Peter J. Hesketh
Keyword(s):  
Power Generation ◽  
Fuel Cell ◽  
Delivery System ◽  
Processing Temperature ◽  
Surface Micromachining ◽  
Fuel Delivery ◽  
Valve Assembly ◽  
Cmos Compatible

This report presents a complete package for bistable electromagnetic actuated microvalve. The function of the valve is to control the fuel delivery system in a fuel cell unit for power generation [1,2]. The microvalves were fabricated on top of a single wafer using 8 masking steps. The fabrication processes have a maximum processing temperature of 300 °C, providing potentially a CMOS compatible process. The valve arrays that compromise of 12 valves per 12 MM × 12 MM chip are built completely by surface micromachining. The chip is assembled into a package with fluidic connection parts. The parts were made from the stereo lithography (SLA) frame that was filled with PDMS. The PDMS also acts as a gasket to seal the microvalve from leaking. The fluidic tests show that the whole valve assembly can stand from leaks up to the pressure of 57.4 kPa.

Control of Stress in a Metal–Nitride–Metal Sandwich for CMOS-Compatible Surface Micromachining

2003 ◽  
Vol 782 ◽  
Author(s):  
Rhodri R. Davies ◽  
David J. Combes ◽  
Mark E. McNie ◽  
Kevin M Brunson
Keyword(s):  
Plane Stress ◽  
Stress Gradient ◽  
Nitride Layer ◽  
Surface Micromachining ◽  
Metal Nitride ◽  
Stress Components ◽  
Out Of Plane ◽  
Curvature Measurements ◽  
Cmos Compatible ◽  
Structural Layer

ABSTRACTFurther to previous work, which demonstrated the ability to engineer the in- and out-of-plane stress components in PECVD silicon nitride, this paper reports on the control of stress in a metal-nitride-metal sandwich. The addition of a symmetric metallisation to the core nitride layer provides additional functionality by enabling electrical connectivity and electrostatic transduction. This represents a widely applicable structural layer for CMOS-compatible surface micromachining.The use of advanced test structures coupled with wafer curvature measurements has allowed for detailed analysis of the stress components within the metal-nitride-metal sandwich and enables predictive engineering of the mechanical properties of the structural layer. Relationships between the in- and out-of-plane stress components of the metal-nitride-metal sandwich as a function of the nitride RF deposition power are reported and discussed. In comparison to values measured for nitride-only, a -30MPa/μm stress gradient offset is observed. A mechanism for the decrease in the stress gradient with the addition of the metallisation is proposed and compares well to modelling.The optimised metal-nitride-metal sandwich can be repeatably engineered to realise low tensile in-plane stress (100MPa) and low out-of-plane stress gradient (0 ± 10MPa/μm). The effective Young's Modulus of the metal-nitride-metal sandwich was determined to be 150GPa; and a value of 195GPa was calculated for the nitride layer using analytical modelling. Work to further reduce the in-plane stress whilst maintaining low stress gradient is in progress by independently tuning the strain of the metal layers.

In-Plane High-Sensitivity Capacitive Accelerometer in a 3-D CMOS-Compatible Surface Micromachining Process

2019 ◽  
Vol 28 (1) ◽  
pp. 14-24
Author(s):  
Ahmad Alfaifi ◽  
Ibrahim A. Alhomoudi ◽  
Frederic Nabki ◽  
Mourad N. El-Gamal
Keyword(s):  
High Sensitivity ◽  
Surface Micromachining ◽  
Capacitive Accelerometer ◽  
Cmos Compatible

Pressure Sensor Monolithically Integrating MEMS and CMOS-LSI with CMOS Compatible “Back-end-of-line MEMS processes”

2010 ◽  
Vol 130 (5) ◽  
pp. 170-175
Author(s):  
Tsukasa Fujimori ◽  
Hideaki Takano ◽  
Yuko Hanaoka ◽  
Yasushi Goto
Keyword(s):  
Pressure Sensor ◽  
Cmos Compatible

Utilizing Nanoprobing and Circuit Diagnostics to Identify Key Failure Mechanism of Otherwise Nonvisible Defects in 20 nm Logic Devices

2014 ◽  
Author(s):  
M.K. Dawood ◽  
C. Chen ◽  
P.K. Tan ◽  
S. James ◽  
P.S. Limin ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Contact Layer ◽  
Fault Isolation ◽  
Tem Analysis ◽  
Logic Devices ◽  
Technology Advancement ◽  
Transmission Electron ◽  
Voltage Contrast ◽  
Almost All ◽  
20 Nm

Abstract In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.

An Introduction to Surface-Micromachining

2004 ◽  
Author(s):  
Robert W. Johnstone ◽  
M. Parameswaran
Keyword(s):  
Surface Micromachining
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