Characterization and Applicatons of Arsenic-Implanted Mocvd-Grown GaAs Structures

1993 ◽  
Vol 316 ◽  
Author(s):  
Fereydoon Namavar ◽  
N. Kalkhoran ◽  
A. Cremins ◽  
S. Vernon
Keyword(s):  
Surface Passivation ◽  
Field Effect Transistors ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Buffer Layers ◽  
Oxide Semiconductor ◽  
High Resistivity ◽  
High Electron ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor

ABSTRACTArsenic precipitates can be formed in GaAs using arsenic implantation and annealing, thereby producing very high resistivity (surface or buried) GaAs layers. Arsenic-implanted materials are similar to low-temperature (LT) GaAs:As buffer layers grown by molecular beam epitaxy (MBE) which are used for eliminating side- and backgating problems in GaAs circuits. Arsenic implantation is not only a simple and economical technique for device isolation but also can improve the quality of individual devices. Through surface passivation, arsenic implantation can reduce gate-to-drain leakage in and enhance the breakdown voltage of GaAs-based metal semiconductor field-effect transistors (MESFETs) and high electron mobility transistors (HEMTs). High resistivity thin surface layers may be used as gate insulators for GaAs-based metal insulator semiconductor (MIS) FETs, leading to the development of a novel GaAs-based complementary metal insulator semiconductor (CMIS) technology like advanced Si-based complementary metal oxide semiconductor (CMOS) technology but with higher radiation hardness and operational speed.

High Electron Mobility Metal–Insulator–Semiconductor Field-Effect Transistors Fabricated on (111)-Oriented InGaAs Channels

2009 ◽  
Vol 2 (12) ◽  
pp. 121101 ◽  
Author(s):  
Hiroyuki Ishii ◽  
Noriyuki Miyata ◽  
Yuji Urabe ◽  
Taro Itatani ◽  
Tetsuji Yasuda ◽  
...  
Keyword(s):  
Electron Mobility ◽  
Field Effect ◽  
Field Effect Transistors ◽  
High Electron ◽  
Metal Insulator ◽  
High Electron Mobility ◽  
Metal Insulator Semiconductor

Fabrication of novel self-aligned metal insulator semiconductor field effect transistors (MISFETs) on InP by a S interface engineering technique

1992 ◽  
Vol 70 (10-11) ◽  
pp. 1035-1038 ◽  
Author(s):  
Chetlur S. Sundararaman ◽  
John F. Currie
Keyword(s):  
Field Effect ◽  
Surface Passivation ◽  
Field Effect Transistors ◽  
Interface State ◽  
Fabrication Process ◽  
Interface Engineering ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
State Densities ◽  
First Time

In this paper we demonstrate for the first time that self-aligned metal insulator semiconductor field effect transistors (MISFETs) can be realized on InP by incorporating an effective surface passivation technique in the fabrication process. A chemical sulfur treatment is used to passivate the InP – indirect plasma silicon nitride interface that results in interface state densities (Dit) in the low 1011/cm2 eV. It is observed that while passivated self-aligned MISFETs subjected to post-passivation high-temperature process cycles up to 700 °C exhibit acceptable transistor characteristics, unpassivated MISFETs using the same process do not show any transistor action. The passivation procedure has been successfully used to demonstrate for the first time a self-aligned InP–InGaAs–InP heterojunction insulated gate FET. We conclude from this work that interface engineering techniques like the one used in this study would be essential to realize and (or) improve the performance of self-aligned FET structures based on InP. The fabrication process described here can be directly applied to similar interface engineering techniques.

Characteristics Research of Hall Magnetic Sensor Based on Nano-Polysilicon Thin Film Transistors

2014 ◽  
Vol 609-610 ◽  
pp. 1082-1087
Author(s):  
Cui Cui Zhuang ◽  
Xiao Feng Zhao ◽  
Yu Song ◽  
Dian Zhong Wen ◽  
Jian Dong Jin ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Thin Film Transistors ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Channel Length ◽  
Magnetic Sensors ◽  
Oxide Semiconductor ◽  
High Resistivity

In this paper, we presented Hall magnetic sensors based on nano-polysilcon thin film transistors(TFTs). These sensors are fabricated on the <100> orientation high resistivity silicon substratesby using complementary metal oxide semiconductor (CMOS) technology and adopting thenano-polysilicon thin films with thickness of 82 nm as the channel layers of TFTs. The influence ofthe channel layer doping type and channel length-width radio of TFT on sensor's sensitivity was investigated.When the supply voltage is 5.0 V, the maximum measured sensitivity of p-type channel andn-type channel sensors are about 8.5 mV/T and 25.6 mV/T, respectively. These experimental resultsmean that nano-polysilicon thin films present an application on Hall magnetic sensors.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

Computational study of the staircase molecular conductivity of polyoxovanadates adsorbed on Au(111)

2021 ◽  
Vol 50 (16) ◽  
pp. 5540-5551
Author(s):  
Almudena Notario-Estévez ◽  
Xavier López ◽  
Coen de Graaf
Keyword(s):  
Metal Oxide ◽  
Computational Study ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Molecular Conduction ◽  
Conduction Properties ◽  
Molecular Conductivity

This computational study presents the molecular conduction properties of polyoxovanadates V6O19 (Lindqvist-type) and V18O42, as possible successors of the materials currently in use in complementary metal–oxide semiconductor (CMOS) technology.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Deep-Submicron Single-Gate Complementary Metal Oxide Semiconductor (CMOS) Technology Using Channel Preamorphization

1998 ◽  
Vol 37 (Part 1, No. 3B) ◽  
pp. 1050-1053 ◽  
Author(s):  
Masayasu Miyake ◽  
Toshio Kobayashi ◽  
Yutaka Sakakibara ◽  
Kimiyoshi Deguchi ◽  
Mitsutoshi Takahashi
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor
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