Development and reliability studies of stencil printing solder-bumped flip chip technology

2002 ◽  
Author(s):  
Jingfeng Gong
Keyword(s):  
Flip Chip ◽  
Stencil Printing ◽  
Chip Technology

Fine pitch stencil printing of Sn/Pb and lead free solders for flip chip technology

1998 ◽  
Vol 21 (1) ◽  
pp. 41-50 ◽  
Author(s):  
J. Kloeser ◽  
K. Heinricht ◽  
K. Kutzner ◽  
E. Jung ◽  
A. Ostmann ◽  
...  
Keyword(s):  
Flip Chip ◽  
Lead Free ◽  
Stencil Printing ◽  
Chip Technology ◽  
Fine Pitch ◽  
Lead Free Solders

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

Failure Analysis of Flip-Chip Interconnections Through Acoustic Microscopy

1996 ◽  
Author(s):  
O. Diaz de Leon ◽  
M. Nassirian ◽  
C. Todd ◽  
R. Chowdhury
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Flip Chip ◽  
Ultrasonic Waves ◽  
Acoustic Microscopy ◽  
Acoustic Microscope ◽  
Chip Technology ◽  
Ball Joints ◽  
Non Destructive ◽  
Scanning Acoustic Microscope

Abstract Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.

scholarly journals Design and Switching Characteristics of Flip-Chip GaN Half-Bridge Modules Integrated with Drivers

2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  
Keyword(s):  
Flip Chip ◽  
High Electron Mobility Transistors ◽  
Wire Bonding ◽  
High Electron ◽  
Parasitic Inductance ◽  
Switching Performance ◽  
Turn On ◽  
Electron Mobility Transistors ◽  
Chip Technology ◽  
Switching Characteristics

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.

Monolithic Thin Film Red LED Active-matrix Micro-display by Flip-chip Technology

2021 ◽  
pp. 1-1
Author(s):  
Peian Li ◽  
Xu Zhang ◽  
Wing Cheung Chong ◽  
Kei May Lau
Keyword(s):  
Thin Film ◽  
Flip Chip ◽  
Active Matrix ◽  
Chip Technology ◽  
Red Led

Research on COB-LED light source with tunable CCT based on screen printing and flip chip technology

2022 ◽  
Vol 54 (2) ◽  
Author(s):  
Rongrong Zhang ◽  
Zuojie Wen ◽  
Bingqian Li ◽  
Shenghua Liang ◽  
Mingde Yang ◽  
...  
Keyword(s):  
Light Source ◽  
Screen Printing ◽  
Flip Chip ◽  
Led Light ◽  
Chip Technology

A Study of the Aperture Filling Process in Solder Paste Stencil Printing

1999 ◽  
Author(s):  
Jianbiao Pan ◽  
Gregory L. Tonkay
Keyword(s):  
Flip Chip ◽  
Deposition Process ◽  
Area Ratio ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Surface Mount ◽  
Fine Pitch ◽  
Main Indicator ◽  
Advanced Packaging

Abstract Stencil printing has been the dominant method of solder deposition in surface mount assembly. With the development of advanced packaging technologies such as ball grid array (BGA) and flip chip on board (FCOB), stencil printing will continue to play an important role. However, the stencil printing process is not completely understood because 52–71 percent of fine and ultra-fine pitch surface mount assembly defects are printing process related (Clouthier, 1999). This paper proposes an analytical model of the solder paste deposition process during stencil printing. The model derives the relationship between the transfer ratio and the area ratio. The area ratio is recommended as a main indicator for determining the maximum stencil thickness. This model explains two experimental phenomena. One is that increasing stencil thickness does not necessarily lead to thicker deposits. The other is that perpendicular apertures print thicker than parallel apertures.

Sign in / Sign up

Export Citation Format

Share Document