Low power VLSI architectures for video applications

Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11556930_19 ◽

2005 ◽

pp. 177-186 ◽

Cited By ~ 2

Author(s):

Th. Giannopoulos ◽

Vassilis Paliouras

Keyword(s):

Low Power ◽

Papr Reduction ◽

Vlsi Architectures

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VLSI architectures for high speed and low power implementation of 5/3 lifting discrete wavelet transform

International Journal of Computational Science and Engineering ◽

10.1504/ijcse.2016.076213 ◽

2016 ◽

Vol 12 (2/3) ◽

pp. 254

Author(s):

N. Usha Bhanu ◽

A. Chilambuchelvan

Keyword(s):

Wavelet Transform ◽

Low Power ◽

Discrete Wavelet Transform ◽

High Speed ◽

Discrete Wavelet ◽

Vlsi Architectures

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Reduced bit low power VLSI architectures for motion estimation

Journal of Systems Engineering and Electronics ◽

10.1109/jsee.2013.00047 ◽

2013 ◽

Vol 24 (3) ◽

pp. 382-399 ◽

Cited By ~ 3

Author(s):

Shahrukh Agha ◽

Shahid Khan ◽

Shahzad Malik ◽

Raja Riaz

Keyword(s):

Motion Estimation ◽

Low Power ◽

Vlsi Architectures

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Low-Power VLSI Architectures for Error Control Coding and Wavelets

10.21236/ada398592 ◽

2001 ◽

Author(s):

Keshab K. Parhi

Keyword(s):

Low Power ◽

Error Control ◽

Error Control Coding ◽

Vlsi Architectures

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A comparative analysis for low power motion estimation VLSI architectures

2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528) ◽

10.1109/sips.2000.886713 ◽

2002 ◽

Cited By ~ 14

Author(s):

M.A. Elgamel ◽

A.M. Shams ◽

M.A. Bayoumi

Keyword(s):

Comparative Analysis ◽

Motion Estimation ◽

Low Power ◽

Vlsi Architectures

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Low power VLSI architectures for variable-length encoding and decoding

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg ◽

10.1109/mwscas.1997.662244 ◽

2005 ◽

Cited By ~ 5

Author(s):

S. Molloy ◽

R. Jain

Keyword(s):

Low Power ◽

Variable Length ◽

Vlsi Architectures

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Low-power VLSI architectures for 3D discrete cosine transform (DCT)

2003 46th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2003.1562597 ◽

2006 ◽

Cited By ~ 2

Author(s):

S. Saponara ◽

L. Fanucci ◽

P. Terreni

Keyword(s):

Low Power ◽

Discrete Cosine Transform ◽

Cosine Transform ◽

Vlsi Architectures

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Enhanced low power motion estimation VLSI architectures for video compression

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196) ◽

10.1109/iscas.2001.922277 ◽

2002 ◽

Author(s):

M.A. Elgamel ◽

A.M. Shams ◽

Xi Xueling ◽

M.A. Bayoumi

Keyword(s):

Motion Estimation ◽

Low Power ◽

Video Compression ◽

Vlsi Architectures

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Low power design of an acoustic echo canceller Gmdfα algorithm on dedicated VLSI architectures

Proceedings Ninth Great Lakes Symposium on VLSI ◽

10.1109/glsv.1999.757447 ◽

2003 ◽

Author(s):

S. Gailhard ◽

N. Julien ◽

A. Baganne ◽

E. Martin

Keyword(s):

Low Power ◽

Low Power Design ◽

Echo Canceller ◽

Vlsi Architectures ◽

Acoustic Echo

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Low power high throughput reconfigurable stream cipher hardware VLSI architectures

International Journal of Information and Computer Security ◽

10.1504/ijics.2014.059785 ◽

2014 ◽

Vol 6 (1) ◽

pp. 1 ◽

Cited By ~ 1

Author(s):

R. Sakthivel ◽

M. Vanitha ◽

Harish M. Kittur

Keyword(s):

Low Power ◽

High Throughput ◽

Stream Cipher ◽

Vlsi Architectures

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