Enhanced low power motion estimation VLSI architectures for video compression

2002 ◽  
Author(s):  
M.A. Elgamel ◽  
A.M. Shams ◽  
Xi Xueling ◽  
M.A. Bayoumi
Keyword(s):  
Motion Estimation ◽  
Low Power ◽  
Video Compression ◽  
Vlsi Architectures

Reduced bit low power VLSI architectures for motion estimation

2013 ◽  
Vol 24 (3) ◽  
pp. 382-399 ◽  
Author(s):  
Shahrukh Agha ◽  
Shahid Khan ◽  
Shahzad Malik ◽  
Raja Riaz
Keyword(s):  
Motion Estimation ◽  
Low Power ◽  
Vlsi Architectures

LOW POWER FULL SEARCH BLOCK MATCHING MOTION ESTIMATION VLSI ARCHITECTURES

2004 ◽  
Vol 13 (06) ◽  
pp. 1271-1288 ◽  
Author(s):  
MOHAMED A. ELGAMEL ◽  
MAGDY A. BAYOUMI ◽  
AHMED M. SHAMS ◽  
BERTRAND ZAVIDOVIQUE
Keyword(s):  
Power Consumption ◽  
Motion Estimation ◽  
Low Power ◽  
Block Matching ◽  
Huge Amount ◽  
Analytical Analysis ◽  
Vlsi Architectures ◽  
Simulation Results ◽  
Full Search ◽  
Low Power Architectures

Power consumption is very critical for portable video applications. During compression, the motion estimation unit consumes the largest portion of power since it performs a huge amount of computation. Different low power architectures for implementing the full-search block-matching (FSBM) motion estimation are discussed. Also, architectural enhancements to further reduce the power consumed during FSBM motion estimation without sacrificing throughput or optimality are presented. The proposed approach achieves these power savings by disabling portions of the architecture that perform unnecessary computations. A comparison between the different architectures including our enhancements and others is presented using simulation and analytical analysis. Different benchmarks are used to test and compare the discussed architectures. Analytical and simulation results show the effectiveness of the enhancements.

Low-Power Motion Estimation Processor with 3D Stacked Memory

2015 ◽  
Vol E98.A (7) ◽  
pp. 1431-1441 ◽  
Author(s):  
Shuping ZHANG ◽  
Jinjia ZHOU ◽  
Dajiang ZHOU ◽  
Shinji KIMURA ◽  
Satoshi GOTO
Keyword(s):  
Motion Estimation ◽  
Low Power ◽  
Stacked Memory

Adaptive Return Prediction Block Matching Algorithms for Video Coding

2011 ◽  
Vol 145 ◽  
pp. 277-281
Author(s):  
Vaci Istanda ◽  
Tsong Yi Chen ◽  
Wan Chun Lee ◽  
Yuan Chen Liu ◽  
Wen Yen Chen
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
Web Site ◽  
Motion Vector ◽  
Temporal Correlation ◽  
Block Matching ◽  
Asynchronous Learning ◽  
Learning And Teaching ◽  
Block Motion ◽  
Reconstruction Image

As the development of network learning, video compression is important for both data transmission and storage, especially in a digit channel. In this paper, we present the return prediction search (RPS) algorithm for block motion estimation. The proposed algorithm exploits the temporal correlation and characteristic of returning origin to obtain one or two predictive motion vector and selects one motion vector, which presents better result, to be the initial search center. In addition, we utilize the center-biased block matching algorithms to refine the final motion vector. Moreover, we used adaptive threshold technique to reduce the computational complexity in motion estimation. Experimental results show that RPS algorithm combined with 4SS, BBGDS, and UCBDS effectively improves the performance in terms of mean-square error measure with less average searching points. On the other hand, accelerated RPS (ARPS) algorithm takes only 38% of the searching computations than 3SS algorithm, and the reconstruction image quality of the ARPS algorithm is superior to 3SS algorithm about 0.30dB in average overall test sequences. In addition, we create an asynchronous learning environment which provides students and instructors flexibility in learning and teaching activities. The purpose of this web site is to teach and display our researchable results. Therefore, we believe this web site is one of the keys to help the modern student achieve mastery of complex Motion Estimation.

scholarly journals Low Power Digital Multimedia Telecommunication Designs

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 301-315 ◽  
Author(s):  
Koon-Shik Cho ◽  
Jun-Dong Cho
Keyword(s):  
Motion Estimation ◽  
Low Power ◽  
Communication Systems ◽  
Matched Filter ◽  
Optimization Technique ◽  
Low Power Design ◽  
Multimedia Systems ◽  
Wireless Multimedia ◽  
Design Constraint ◽  
Power Capability

The increasing prominence of wireless multimedia systems and the need to limit power capability in very-high density VLSI chips have led to rapid and innovative developments in low-power design. Power reduction has emerged as a significant design constraint in VLSI design. The need for wireless multimedia systems leads to much higher power consumption than traditional portable applications. This paper presents possible optimization technique to reduce the energy consumption for wireless multimedia communication systems. Four topics are presented in the wireless communication systems subsection which deal with architectures such as PN acquisition, parallel correlator, matched filter and channel coding. Two topics include the IDCT and motion estimation in multimedia application.These topics consider algorithms and architectures for low power design such as using hybrid architecture in PN acquisition, analyzing the algorithm and optimizing the sample storage in parallel correlator, using complex matched filter that analog operational circuits controlled by digital signals, adopting bit serial arithmetic for the ACS operation in viterbi decoder, using CRC to adaptively terminate the SOVA iteration in turbo decoder, using codesign in RS codec, disabling the processing elements as soon as the distortion values become great than the minimum distortion value in motion estimation, and exploiting the relative occurrence of zero-valued DCT coefficient in IDCT.

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