Modeling and characterization of deep submicron devices on fully depleted silicon-on-insulator technology

1996 ◽  
Author(s):  
Srinivasa Rao Banna
Keyword(s):  
Deep Submicron ◽  
Silicon On Insulator ◽  
Fully Depleted ◽  
Submicron Devices ◽  
Silicon On Insulator Technology

Advantages of Faceted P-Raised Source/Drain in Fully Depleted Silicon on Insulator Technology

2018 ◽  
Vol 86 (7) ◽  
pp. 199-206 ◽  
Author(s):  
Ömür Işıl Aydin ◽  
Judson Robert Holt ◽  
Cyrille Le Royer ◽  
Laks Vanamurthy ◽  
Thomas Feudel ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
Silicon On Insulator Technology

A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology

2016 ◽  
Vol 117 ◽  
pp. 100-116 ◽  
Author(s):  
Pierre Morin ◽  
Sylvain Maitrejean ◽  
Frederic Allibert ◽  
Emmanuel Augendre ◽  
Qing Liu ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Thin Body ◽  
Fully Depleted ◽  
Buried Oxide ◽  
Silicon On Insulator Technology

Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology

2016 ◽  
Vol 12 (1) ◽  
pp. 64-73 ◽  
Author(s):  
Zhaopeng Wei ◽  
Gilles Jacquemod ◽  
Philippe Lorenzini ◽  
Frederic Hameau ◽  
Emeric de Foucauld ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Fully Depleted ◽  
Silicon On Insulator Technology ◽  
28 Nm

Silicidation Strategy Of Sub-0.1 μm Junctions for Deep Submicron Devices

1995 ◽  
Vol 402 ◽  
Author(s):  
Jiunn-Yann Tsai ◽  
Carlton M. Osburn ◽  
Steve L. Hsia
Keyword(s):  
Series Resistance ◽  
Deep Submicron ◽  
Silicon On Insulator ◽  
Promising Alternative ◽  
Resistance Increase ◽  
Low Leakage ◽  
Submicron Devices ◽  
Diffusion Source ◽  
Ultra Shallow Junctions ◽  
Silicon Interface

AbstractTwo major concerns for silicidation of ultra-shallow junctions, namely the silicon-consumption- induced junction leakage and the series resistance increase, were compared among conventional post-junction-silicide (PJS) contact, silicide-as-a-diffusion-source (SADS) contact, Silicon-On-Insulator (SOI) contact, and elevated-source-drain (ESD) contact. Even though we found that ESD contacts would be the ultimate solution for both problems, SOI and SADS contacts provide better resistance to silicon-consumption-induced series resistance increase over conventional PJS contact because both are able to maintain a high dopant concentration at the silicide/silicon interface and thus a low specific contact resistivity. While there is no junction leakage concern for SOI contact, the SADS junction is also distinguished by low leakage owing to its lack of implant damage in the silicon substrate and uniformly doped junction along the silicide/silicon interface contour. MOSFET devices with SADS source/drain were demonstrated with quarter-μm technology. Epitaxial cobalt disilicide (CoSi2) was formed using the Ti/Co bilayer technique as a diffusion source. While both ESD and SOI processes still suffer from process complexity, integration and materials issues, we conclude that SADS contacting is a promising alternative for deep submicron devices.

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