scholarly journals Parity Codes Used for On-Line Testing in FPGA

10.14311/788 ◽  
2005 ◽  
Vol 45 (6) ◽  
Author(s):  
P. Kubalík ◽  
H. Kubátová
Keyword(s):  
Error Detection ◽  
Digital Circuits ◽  
Fault Model ◽  
Concurrent Error Detection ◽  
Combinational Circuit ◽  
Safe Operation ◽  
On Line ◽  
Xilinx Fpga ◽  
Eda Tools

This paper deals with on-line error detection in digital circuits implemented in FPGAs. Error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit must be detected and signalized at the time of its appearance and before further distribution of errors. Hence safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. Combinational circuit benchmarks have been used in this work in order to compute the quality of the proposed codes. The description of the benchmarks is based on equations and tables. All of our experimental results are obtained by XILINX FPGA implementation EDA tools. A possible TSC structure consisting of several TSC blocks is presented. 

scholarly journals Scalable PP-1 block cipher

2010 ◽  
Vol 20 (2) ◽  
pp. 401-411 ◽  
Author(s):  
Krzysztof Bucholc ◽  
Krzysztof Chmiel ◽  
Anna Grocholewska-Czuryło ◽  
Ewa Idzikowska ◽  
Izabela Janicka-Lipska ◽  
...  
Keyword(s):  
Error Detection ◽  
Processing Speed ◽  
Block Cipher ◽  
Limited Resources ◽  
Concurrent Error Detection ◽  
Test Results ◽  
Speed Test ◽  
Fast Arithmetic ◽  
Key Scheduling

Scalable PP-1 block cipherA totally involutional, highly scalable PP-1 cipher is proposed, evaluated and discussed. Having very low memory requirements and using only simple and fast arithmetic operations, the cipher is aimed at platforms with limited resources, e.g., smartcards. At the core of the cipher's processing is a carefully designed S-box. The paper discusses in detail all aspects of PP-1 cipher design including S-box construction, permutation and round key scheduling. The quality of the PP-1 cipher is also evaluated with respect to linear cryptanalysis and other attacks. PP-1's concurrent error detection is also discussed. Some processing speed test results are given and compared with those of other ciphers.

scholarly journals On VHDL synthesis of self-checking two-level combinational circuits

2004 ◽  
Vol 17 (1) ◽  
pp. 69-79
Author(s):  
Tatjana Stankovic ◽  
Mile Stojcev ◽  
Goran Djordjevic
Keyword(s):  
Error Detection ◽  
Data Integrity ◽  
Operating Speed ◽  
Concurrent Error Detection ◽  
Combinational Logic ◽  
Combinational Circuits ◽  
Combinational Circuit ◽  
The Third ◽  
Separable Code

Concurrent error detection (CED) is an important technique in the design of system in which dependability and data integrity are important. Using the separable code for CED has the advantage that no decoding is needed to get the normal output bits. In this paper, we address the problem of synthesizing totally self-checking two level combinational circuits starting from a VHDL description. Three schemes for CED are proposed. The first scheme uses duplication of a combinational logic with the addition of a totally self-checking comparator. The second scheme for synthesizing combinational circuits with CED uses Bose-Lin code. The third scheme is based on parity codes on the outputs of a combinational circuit. The area overheads and operating speed decreases for seven combinational circuits of standard architecture are reported in this paper.

The specificities of organization of concurrent error detection systems for combinational circuits based on polynomial codes

2018 ◽  
pp. 432-445
Author(s):  
Valeriy Sapozhnikov ◽  
Vladimir Sapozhnikov ◽  
Dmitriy Efanov ◽  
Ruslan Abdullaev
Keyword(s):  
Error Detection ◽  
Logic Circuits ◽  
Concurrent Error Detection ◽  
Combinational Logic ◽  
Computer Engineering ◽  
Combinational Circuit ◽  
Detection Systems ◽  
Essential Properties ◽  
Combinational Logic Circuits ◽  
Polynomial Codes

Objective: To study the specificities of polynomial codes application during the organization of concurrent error detection systems for combinational logic circuits of automation and computer engineering. Methods: The methods of information theory and coding, the theory of discrete devices and diagnostic engineering of discrete systems were applied. Results: The possibilities of using polynomial codes in the process of combinational logic circuits control organization were analyzed. Some essential properties, inherent in generator polynomials, which make it possible to synthesize self-checking circuits of concurrent error detection systems, were pointed out. Particularly, one of such essential properties is the presence of a constant term in a generator polynomial (otherwise, all the required test patterns are not generated for a complete check of a coding device). An example of concurrent error detection sys- tem implementation for a combinational circuit was given. Some experimental data on error detection in LGSynth’89 combinational benchmarks were described. Practical importance: The use of polynomial codes for combinational circuit control makes it possible to synthesize self-checking discrete devices of automation and computer engineering.

Fault Tolerant Techniques for Finite Field Multipliers

2014 ◽  
Vol 573 ◽  
pp. 209-214
Author(s):  
B. Sargunam ◽  
R. Dhanasekaran
Keyword(s):  
Finite Field ◽  
Error Detection ◽  
Fault Tolerant ◽  
High Reliability ◽  
Concurrent Error Detection ◽  
Polynomial Representation ◽  
Finite Field Multiplier ◽  
On Line ◽  
Error Detecting ◽  
Modular Redundancy

The use of finite field multipliers in the critical applications like elliptic curve cryptography needs Concurrent Error Detection (CED) and correction at architectural level to provide high reliability. This paper discusses fault tolerant technique for polynomial representation based finite field multipliers. The detection and correction are done on-line. We use a combination of Double Modular Redundancy (DMR) and Concurrent Error Detection (CED) techniques. The fault tolerant finite field multiplier is coded in VHDL and simulated using Modelsim. Further, the proposed multiplier with fault tolerant capability is synthesized and results are analyzed with respect to area occupied, input and output pin counts and delay. Our technique, when compared with existing techniques, gives better performance. We show that our concurrent error detecting multiplier over GF(2m) requires less than 200% extra hardware, whereas with the traditional fault tolerant techniques, such as Triple Modular Redundancy (TMR), overhead is more than 200%.

Compaction-based concurrent error detection for digital circuits

2005 ◽  
Vol 36 (9) ◽  
pp. 856-862 ◽  
Author(s):  
Sobeeh Almukhaizim ◽  
Petros Drineas ◽  
Yiorgos Makris
Keyword(s):  
Error Detection ◽  
Digital Circuits ◽  
Concurrent Error Detection

Automatic buffer capacity based sensor for effluent quality monitoring

1996 ◽  
Vol 33 (1) ◽  
pp. 81-87
Author(s):  
L. Van Vooren ◽  
P. Willems ◽  
J. P. Ottoy ◽  
G. C. Vansteenkiste ◽  
W. Verstraete
Keyword(s):  
Wastewater Treatment ◽  
Buffer Capacity ◽  
Wastewater Treatment Plants ◽  
Data Interpretation ◽  
Full Scale ◽  
Quality Monitoring ◽  
Effluent Quality ◽  
Capacity Curves ◽  
On Line

The use of an automatic on-line titration unit for monitoring the effluent quality of wastewater plants is presented. Buffer capacity curves of different effluent types were studied and validation results are presented for both domestic and industrial full-scale wastewater treatment plants. Ammonium and ortho-phosphate monitoring of the effluent were established by using a simple titration device, connected to a data-interpretation unit. The use of this sensor as the activator of an effluent quality proportional sampler is discussed.

Sign in / Sign up

Export Citation Format

Share Document