Concurrent error detection in nonlinear digital circuits using time-freeze linearization

1997 ◽  
Vol 46 (11) ◽  
pp. 1208-1218 ◽  
Author(s):  
A. Chatterjee ◽  
R.K. Roy
10.14311/788 ◽  
2005 ◽  
Vol 45 (6) ◽  
Author(s):  
P. Kubalík ◽  
H. Kubátová

This paper deals with on-line error detection in digital circuits implemented in FPGAs. Error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit must be detected and signalized at the time of its appearance and before further distribution of errors. Hence safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. Combinational circuit benchmarks have been used in this work in order to compute the quality of the proposed codes. The description of the benchmarks is based on equations and tables. All of our experimental results are obtained by XILINX FPGA implementation EDA tools. A possible TSC structure consisting of several TSC blocks is presented. 


2005 ◽  
Vol 36 (9) ◽  
pp. 856-862 ◽  
Author(s):  
Sobeeh Almukhaizim ◽  
Petros Drineas ◽  
Yiorgos Makris

Author(s):  
A. L. Stempkovskiy ◽  
◽  
D. V. Telpukhov ◽  
A. I. Demeneva ◽  
T. D. Zhukova ◽  
...  

1983 ◽  
Vol 11 (3) ◽  
pp. 309-315 ◽  
Author(s):  
W. Kent Fuchs ◽  
Jacob A. Abraham ◽  
Kuang-Hua Huang

2021 ◽  
Vol 190 ◽  
pp. 361-369
Author(s):  
Mikhail Ivanov ◽  
Iliya Chugunkov ◽  
Bogdana Kliuchnikova ◽  
Evgenii Salikov

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