On VHDL synthesis of self-checking two-level combinational circuits

Concurrent error detection (CED) is an important technique in the design of system in which dependability and data integrity are important. Using the separable code for CED has the advantage that no decoding is needed to get the normal output bits. In this paper, we address the problem of synthesizing totally self-checking two level combinational circuits starting from a VHDL description. Three schemes for CED are proposed. The first scheme uses duplication of a combinational logic with the addition of a totally self-checking comparator. The second scheme for synthesizing combinational circuits with CED uses Bose-Lin code. The third scheme is based on parity codes on the outputs of a combinational circuit. The area overheads and operating speed decreases for seven combinational circuits of standard architecture are reported in this paper.

Separable Routes to Human Memory Formation: Dissociating Task and Material Contributions in the Prefrontal Cortex

The present study used fMRI to investigate functional dissociations across frontal regions during incidental memory formation. Subjects were imaged while encoding materials with differential access to phonological codes (nonfamous faces and nameable famous faces) under task conditions that encouraged elaborate (deep) or superficial (shallow) encoding strategies. Results revealed a functional dissociation between dorsal posterior regions of the prefrontal cortex (BA 6/44) that were sensitive to material type (famous vs. nonfamous), irrespective of the encoding task, and ventral anterior regions of the prefrontal cortex (BA 45/47) that were uniquely sensitive to task demands (deep vs. shallow), regardless of material type. Further, subjects realized a memorial advantage to the extent that they recruited these dissociable frontal regions. These results demonstrate a posterior/anterior dichotomy in the frontal cortex that underlies separable code-based routes to human memory formation.