scholarly journals Monitored wet-etch removal of individual dielectric layers from high-finesse Bragg mirrors

2020 ◽  
Vol 28 (23) ◽  
pp. 33823
Author(s):  
Simon Bernard ◽  
Thomas J. Clark ◽  
Vincent Dumont ◽  
Jiaxing Ma ◽  
Jack C. Sankey
Keyword(s):  
Dielectric Layers ◽  
Wet Etch ◽  
High Finesse

Multilayer thin and ultrathin film capacitors fabricated by chemical solution deposition

2008 ◽  
Vol 23 (1) ◽  
pp. 176-181 ◽  
Author(s):  
Geoff L. Brennecka ◽  
Chad M. Parish ◽  
Bruce A. Tuttle ◽  
Luke N. Brewer
Keyword(s):  
Chemical Solution Deposition ◽  
Platinum Electrodes ◽  
Chemical Solution ◽  
Lead Lanthanum Zirconate Titanate ◽  
Solution Deposition ◽  
Passive Components ◽  
Dielectric Layers ◽  
20 Nm ◽  
Wet Etch ◽  
Multilayer Stacks

Chemical solution deposition has been used to fabricate continuous ultrathin lead lanthanum zirconate titanate (PLZT) films as thin as 20 nm. Further, multilayer capacitor structures with as many as 10 dielectric layers have been fabricated from these ultrathin PLZT films by alternating spin-coated dielectric layers with sputtered platinum electrodes. Integrating a photolithographically defined wet etch step to the fabrication process enabled the production of functional multilayer stacks with capacitance values exceeding 600 nF. Such ultrathin multilayer capacitors offer tremendous advantages for further miniaturization of integrated passive components.

Precipitation in silicon: Microanalysis

1988 ◽  
Vol 46 ◽  
pp. 474-475
Author(s):  
R.W. Carpenter
Keyword(s):  
Transition Metals ◽  
Spatial Resolution ◽  
Thin Foil ◽  
Precipitation Reaction ◽  
High Current ◽  
Reaction Products ◽  
Carbon And Nitrogen ◽  
Dielectric Layers ◽  
Precipitation Processes ◽  
Areas Of Interest

Interest in precipitation processes in silicon appears to be centered on transition metals (for intrinsic and extrinsic gettering), and oxygen and carbon in thermally aged materials, and on oxygen, carbon, and nitrogen in ion implanted materials to form buried dielectric layers. A steadily increasing number of applications of microanalysis to these problems are appearing. but still far less than the number of imaging/diffraction investigations. Microanalysis applications appear to be paced by instrumentation development. The precipitation reaction products are small and the presence of carbon is often an important consideration. Small high current probes are important and cryogenic specimen holders are required for consistent suppression of contamination buildup on specimen areas of interest. Focussed probes useful for microanalysis should be in the range of 0.1 to 1nA, and estimates of spatial resolution to be expected for thin foil specimens can be made from the curves shown in Fig. 1.

The effect of an aluminum heat-sink layer on the laser-induced amorphization of SiOx/TeGeSn/SiOx phase-change recording films

1989 ◽  
Vol 47 ◽  
pp. 574-575
Author(s):  
Matthew R. Libera ◽  
Martin Chen
Keyword(s):  
Thin Film ◽  
Phase Change ◽  
Heat Sink ◽  
Multilayer Film ◽  
Glassy Phase ◽  
Film Structure ◽  
Glass Forming ◽  
Active Storage ◽  
Dielectric Layers ◽  
Amorphous States

Phase-change erasable optical storage is based on the ability to switch a micron-sized region of a thin film between the crystalline and amorphous states using a diffraction-limited laser as a heat source. A bit of information can be represented as an amorphous spot on a crystalline background, and the two states can be optically identified by their different reflectivities. In a typical multilayer thin-film structure the active (storage) layer is sandwiched between one or more dielectric layers. The dielectric layers provide physical containment and act as a heat sink. A viable phase-change medium must be able to quench to the glassy phase after melting, and this requires proper tailoring of the thermal properties of the multilayer film. The present research studies one particular multilayer structure and shows the effect of an additional aluminum layer on the glass-forming ability.

Application of KOH Electrochemical Etch and Passive Voltage Contrast Techniques for Deep Sub-Micron CMOS Leaky Gate Detection

2000 ◽  
Author(s):  
Fred Y. Chang ◽  
Victer Chan
Keyword(s):  
Case Studies ◽  
Detection Technique ◽  
Cobalt Silicide ◽  
Process Technology ◽  
Process Flow ◽  
Voltage Contrast ◽  
Emission Detection ◽  
Wet Etch ◽  
Direct Confirmation

Abstract This paper describes a novel de-process flow by combining cobalt silicide / nitride wet etch with KOH electrochemical wet etch (ECW) to identify leaky gate in silicided deep sub-micron process technology. Traditionally, leaky gate identification requires direct confirmation by gate level electrical or emission detection technique. Ohtani [1] used KOH electrochemical etch application to identify nonsilicided leaky gate capacitor in DRAM without using the above confirmation. The result of the case study demonstrates the expanded application of ECW etch to both silicided 0.18um logic and SRAM devices. Voltage contrast at metal 1 to assist leaky gate localization is also proposed. By combining both techniques, the possibility for isolating gate related defects are greatly enhanced. Case studies also show the advantages of the proposed technique over conventional poly level voltage contrast in leaky gate identification especially with devices that use local interconnect and nitride liner process.

A Review of Wet Etch Formulas for Silicon Semiconductor Failure Analysis

1996 ◽  
Author(s):  
T.W. Lee
Keyword(s):  
Failure Analysis ◽  
Literature Search ◽  
Wet Etching ◽  
Second Step ◽  
Environmental Concerns ◽  
Acid System ◽  
Graphical Data ◽  
Selective Etch ◽  
Chromium Compounds ◽  
Wet Etch

Abstract WET ETCHING is an important part of the failure analysis of semiconductor devices. Analysis requires etches for the removal, delineation by decoration or differential etching, and study of defects in layers of various materials. Each lab usually has a collection of favored etch recipes. Some of these etches are available premixed from the fab chemical supply. Some of these etches may be unique, or even proprietary, to your company. Additionally, the lab etch recipe list will usually contain a variety of classical "named etches". These recipes, such as Dash Etch, have persisted over time. Although well-reported in the literature, lab lists may not accurately represent these recipes, or contain complete and accurate instructions for their use. Time seems to have erased the understanding of the purpose of additives such as iodine, in some of these formulas. To identify the best etches and techniques for a failure analysis operations, a targeted literature review of articles and patents was undertaken. It was a surprise to find that much of the work was quite old, and originally done with germanium. Later some of these etches were modified for silicon. Much of this work is still applicable today. Two main etch types were found. One is concerned with the thinning and chemical polishing of silicon. The other type is concerned with identifying defects in silicon. Many of the named etches were found to consist of variations in a specific acid system. The acid system has been well characterized with ternary diagrams and 3-D surfaces. The named etches were plotted on this diagram. The original formulas and applications of the named etches were traced to assure accuracy, so that the results claimed by the original authors, may be reproduced in today's lab. The purpose of this paper is to share the condensed information obtained during this literature search. Graphical data has been corrected for modem dimensions. Selectivities have been located and discussed. The contents of more than 25 named etches were spreadsheeted. It was concluded that the best approach to delineation is a two-step etch, using uncomplicated and well-characterized standard formulas. The first step uses a decoration or differential etch technique to define the junctions. Formulations for effective decoration etches were found to be surprisingly simple. The second step uses a selective etch to define the various interconnections and dielectric layers. Chromium compounds can be completely eliminated from these formulas, to meet environmental concerns. This work, originally consisting of 30 pages with 106 references, has been condensed to conform with the formatting requirements of this publication.

Precision Xe Plasma FIB Delayering for Physical Failure Analysis of Sub-20 nm Microprocessor Devices

2017 ◽  
Author(s):  
D. Zudhistira ◽  
V. Viswanathan ◽  
V. Narang ◽  
J.M. Chin ◽  
S. Sharang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Dielectric Films ◽  
Planar Surface ◽  
Chemical Methods ◽  
Root Cause ◽  
Essential Step ◽  
Dielectric Layers ◽  
Wet Chemical ◽  
20 Nm ◽  
Low K

Abstract Deprocessing is an essential step in the physical failure analysis of ICs. Typically, this is accomplished by techniques such as wet chemical methods, RIE, and mechanical manual polishing. Manual polishing suffers from highly non-uniform delayering particularly for sub 20nm technologies due to aggressive back-end-of-line scaling and porous ultra low-k dielectric films. Recently gas assisted Xe plasma FIB has demonstrated uniform delayering of the metal and dielectric layers, achieving a planar surface of heterogeneous materials. In this paper, the successful application of this technique to delayer sub-20 nm microprocessor chips with real defects to root cause the failure is presented.

Locating Gate Oxide Failures Using KOH

2016 ◽  
Author(s):  
Lori L. Sarnecki
Keyword(s):  
Potassium Hydroxide ◽  
Gate Oxide ◽  
New Technique ◽  
Deep Trench ◽  
New Methods ◽  
Wet Etch

Abstract This paper presents two new methods using potassium hydroxide (KOH) as a wet etch technique to successfully stop on gate oxide and find the submicron gate oxide failures that correspond to failure response sites. Applications of this new technique to submicron gate oxide failures on both planar and deep trench MOSFET devices are reported in this paper.

Deprocessing Methodologies for Detection of IBC and Cell-to-Cell Shorts in Submicron DRAM

2012 ◽  
Author(s):  
Ramachandra Chitakudige ◽  
Sarat Kumar Dash ◽  
A.M. Khan
Keyword(s):  
High Selectivity ◽  
Electron Cyclotron Resonance ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Plasma System ◽  
Poly Silicon ◽  
Hazardous Gases ◽  
Wet Etch ◽  
Resonance Plasma

Abstract Detection of both Insufficient Buried Contact (IBC) and cell-to-cell short defects is quite a challenging task for failure analysis in submicron Dynamic Random Access Memory (DRAM) devices. A combination of a well-controlled wet etch and high selectivity poly silicon etch is a key requirement in the deprocessing of DRAM for detection of these types of failures. High selectivity poly silicon etch methods have been reported using complicated system such as ECR (Electron Cyclotron Resonance) Plasma system. The fact that these systems use hazardous gases like Cl2, HBr, and SF6 motivates the search for safer alternative deprocessing chemistries. The present work describes high selectivity poly silicon etch using simple Reactive Ion Etch (RIE) plasma system using less hazardous gases such as CF4, O2 etc. A combination of controlled wet etch and high selectivity poly silicon etch have been used to detect both IBC and cell-to-cell shorts in submicron DRAMs.

Modified configuration for a high-finesse compact loop resonator for semiconductor integrated optics

1990 ◽  
Vol 26 (18) ◽  
pp. 1528 ◽  
Author(s):  
A. Shahar ◽  
W.J. Tomlinson ◽  
M. Sato
Keyword(s):  
Integrated Optics ◽  
High Finesse

Metal Wet Etch Process Development for Dual Metal Gate CMOS

2005 ◽  
Vol 8 (12) ◽  
pp. G333 ◽  
Author(s):  
Muhammad Mustafa Hussain ◽  
Naim Moumen ◽  
Joel Barnett ◽  
Jason Saulters ◽  
David Baker ◽  
...  
Keyword(s):  
Process Development ◽  
Metal Gate ◽  
Dual Metal ◽  
Wet Etch
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