Limited switch dynamic logic circuits for high-speed low-power circuit design

2006 ◽  
Vol 50 (2.3) ◽  
pp. 277-286 ◽  
Author(s):  
W. Belluomini ◽  
D. Jamsek ◽  
A. K. Martin ◽  
C. McDowell ◽  
R. K. Montoye ◽  
...  
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
High Speed ◽  
Dynamic Logic ◽  
Logic Circuits ◽  
Power Circuit

scholarly journals Research on High Speed Low Power Digital Logic Family for Pipelined Arithmatic Logic Structures

2019 ◽  
Vol 8 (12S) ◽  
pp. 637-648
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
High Speed ◽  
Dynamic Logic ◽  
Structure Design ◽  
Clock Speed ◽  
Design Structure ◽  
Dynamic Structures ◽  
Logic Structures ◽  
Data Length

The bit size of the data length process depends on the clock speed operation .the clock speed increases with the bit size of the data length .but this increases deal in the circuit to overcome this pipeline and parallel processing is used. This will increase the performance of the circuit with the advancement of the high speed technology the data length process per clock is increasing rapidly from Intel 1 intel20 to Intel series. Adder is an important adder structure design which uses parallel and pipelining scheme are RCA and SFA. To design these adders we need high speed processing digital electronic circuit which must be high speed and low power. There are various types of logic families which we are discuss in this paper. From static to dynamic circuit design why dynamic is faster than static. and various types of dynamic circuit design structure this paper basically focus on constant delay logic style and why it is superior to other dynamic structures such as domino logic ,dynamic logic np CMOS logic,C2MOS logic ,NORA CMOS logic design, Zipper CMOS,FTL logic.

scholarly journals Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL)

2018 ◽  
Vol 7 (3) ◽  
pp. 1548
Author(s):  
P Sasipriya ◽  
V S Kanchana Bhaaskaran
Keyword(s):  
Low Power ◽  
High Speed ◽  
Dynamic Logic ◽  
Logic Circuits ◽  
Clock Signal ◽  
Two Phase ◽  
Industry Standard ◽  
Look Ahead ◽  
Adiabatic Logic ◽  
Sequential Logic

This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate the energy efficiency of the proposed logic, an 8-bit pipelined carry look-ahead (CLA) adder is designed using CCDAL and it is also compared against the other high speed two phase counterpart available in the literature and conventional static CMOS. The simulation results show that the CCDAL logic can operate efficiently at high frequencies compared to other two phase adiabatic logic circuits. All the circuits have been designed using UMC 90nm technology library and the simulations are carried out using industry standard Cadence® Virtuoso tool.  

LOW-POWER, PARALLEL INTERFACE WITH CONTINUOUS-TIME ADAPTIVE PASSIVE EQUALIZER AND CROSSTALK CANCELLATION

2005 ◽  
Vol 15 (02) ◽  
pp. 459-476
Author(s):  
C. PATRICK YUE ◽  
JAEJIN PARK ◽  
RUIFENG SUN ◽  
L. RICK CARLEY ◽  
FRANK O'MAHONY
Keyword(s):  
Low Power ◽  
Electromagnetic Interference ◽  
Continuous Time ◽  
High Speed ◽  
High Performance ◽  
Process Variations ◽  
Cmos Process ◽  
Power Circuit ◽  
Crosstalk Cancellation ◽  
Circuit Components

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.

Seek-method based 2’s complement circuit for low power circuit and high-speed operation

2021 ◽  
Author(s):  
S. Deepak ◽  
Ganesan. SaiKrishnan ◽  
D. Rajesh ◽  
J. V. R. Ravindra
Keyword(s):  
Low Power ◽  
High Speed ◽  
Power Circuit

Low-Power Circuit Design for Cardiac Data Mining in Medical Sensor Networks

2010 ◽  
pp. 853-882
Author(s):  
Fei Hu ◽  
Alexandru Samachisa ◽  
Marcin Lukowiak ◽  
Daniel Philips ◽  
Yang Xiao
Keyword(s):  
Data Mining ◽  
Sensor Networks ◽  
Low Power ◽  
Circuit Design ◽  
Power Circuit ◽  
Medical Sensor Networks
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