scholarly journals The Effect of Silicon Wafer Substrate Micro Roughness on the Surface Particles of the Epitaxial Silicon Wafers

2018 ◽  
Vol 08 (05) ◽  
pp. 530-534
Author(s):  
而敬 赵
Keyword(s):  
Silicon Wafer ◽  
Silicon Wafers ◽  
Epitaxial Silicon ◽  
Wafer Substrate

Enhanced Internal Gettering of Iron in n/n+ Epitaxial Silicon Wafer: Effect of High Temperature Rapid Thermal Annealing in Nitrogen Ambient

2015 ◽  
Vol 242 ◽  
pp. 218-223
Author(s):  
Peng Dong ◽  
Xing Bo Liang ◽  
Da Xi Tian ◽  
Xiang Yang Ma ◽  
De Ren Yang
Keyword(s):  
Silicon Wafer ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Silicon Wafers ◽  
Enhancement Effect ◽  
Epitaxial Silicon ◽  
High Concentration ◽  
Oxygen Precipitation ◽  
Doped Silicon ◽  
The One

We report a strategy feasible for improving the internal gettering (IG) capability of iron (Fe) for n/n+ epitaxial silicon wafers using the heavily arsenic (As)-doped Czochralski (CZ) silicon wafers as the substrates. The n/n+ epitaxial silicon wafers were subjected to the two-step anneal of 650 °C/16 h + 1000 °C/16 h following the rapid thermal processing (RTP) at 1250 °C in argon (Ar) or nitrogen (N2) atmosphere. It is found that the prior RTP in N2 atmosphere exhibits much stronger enhancement effect on oxygen precipitation (OP) in the substrates than that in Ar atmosphere, thereby leading to a better IG capability of Fe contamination on the epitaxial wafer. In comparison with the RTP in Ar atmosphere, the one in N2 atmosphere injects not only vacancies but also nitrogen atoms of high concentration into the heavily As-doped silicon substrate. The co-action of vacancy and nitrogen leads to the enhanced OP in the substrate and therefore the better IG capability for the n/n+ epitaxial silicon wafer.

Hydrophobic Silicon-Direct Bonding for Fabrication of RF Microwave Devices

Manufacturing ◽  
2003 ◽  
Author(s):  
Iqbal K. Bansal
Keyword(s):  
Silicon Wafer ◽  
Failure Modes ◽  
Elevated Temperatures ◽  
Silicon Wafers ◽  
Electrical Performance ◽  
High Resistivity ◽  
Wafer Surface ◽  
Scanning System ◽  
Epitaxial Silicon ◽  
Thermal Bonding

Direct wafer bonding (DWB) is an operation of ultra-fine alignment, joining and thermal bonding of two silicon wafers. The first silicon wafer “handle” substrate is a Czochralski (<CZ>) substrate with N+ arsenic dopant with very low bulk resistivity, whereas second wafer “device” is a float-zone (<FZ>) having extremely high resistivity N-phosphorus dopant. Prior to the joining step, silicon wafers are chemically cleaned in order to minimize surface contamination. The wafer surface is “hydrophobic” which is achieved using an insitu oxide etching process. The surface quality is also characterized in terms of sub-micron light point defects (LPD’s) counts and haze concentration using a laser beam scanning system. After chemical clean, none of the LPD’s counts is greater than 1.0 μ size. The joining step is performed in a Class 100 or better environment by employing a commercial joiner. Then, thermal bonding operation is carried out by employing an extended stream oxidation cycle at elevated temperatures. Typical failure modes of DWB are misalignment errors and “voided” or “disbonded” regions. The area of “voided” regions for each bonded pair is determined by employing a scanning acoustic microscope. Detailed product throughtput and yield data are presented in this paper. A spreading resistivity profile (SRP) system is employed for accurate measurement of doping carrier concentration as a function of the depth. The superior uniformity for capacitance-voltage characteristics of a Si-Si bonded wafer versus an inverse epitaxial silicon wafer substrate is shown in terms of the device performance. The applications of silicon-direct wafer bonded substrates provide a quantum jump in the device electrical performance of PIN diodes.

scholarly journals The Influence of Wire Speed on Phase Transitions and Residual Stress in Single Crystal Silicon Wafers Sawn by Resin Bonded Diamond Wire Saw

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 429
Author(s):  
Tengyun Liu ◽  
Peiqi Ge ◽  
Wenbo Bi
Keyword(s):  
Residual Stress ◽  
Surface Layer ◽  
Phase Transitions ◽  
Single Crystal ◽  
Amorphous Silicon ◽  
Silicon Wafer ◽  
Single Crystal Silicon ◽  
Silicon Wafers ◽  
Crystal Silicon ◽  
Diamond Wire

Lower warp is required for the single crystal silicon wafers sawn by a fixed diamond wire saw with the thinness of a silicon wafer. The residual stress in the surface layer of the silicon wafer is the primary reason for warp, which is generated by the phase transitions, elastic-plastic deformation, and non-uniform distribution of thermal energy during wire sawing. In this paper, an experiment of multi-wire sawing single crystal silicon is carried out, and the Raman spectra technique is used to detect the phase transitions and residual stress in the surface layer of the silicon wafers. Three different wire speeds are used to study the effect of wire speed on phase transition and residual stress of the silicon wafers. The experimental results indicate that amorphous silicon is generated during resin bonded diamond wire sawing, of which the Raman peaks are at 178.9 cm−1 and 468.5 cm−1. The ratio of the amorphous silicon surface area and the surface area of a single crystal silicon, and the depth of amorphous silicon layer increases with the increasing of wire speed. This indicates that more amorphous silicon is generated. There is both compressive stress and tensile stress on the surface layer of the silicon wafer. The residual tensile stress is between 0 and 200 MPa, and the compressive stress is between 0 and 300 MPa for the experimental results of this paper. Moreover, the residual stress increases with the increase of wire speed, indicating more amorphous silicon generated as well.

Experimental investigation into polishing of monocrystalline silicon wafer using double-disc chemical assisted magnetorheological finishing process

2021 ◽  
pp. 095440622098384
Author(s):  
Mayank Srivastava ◽  
Pulak M Pandey
Keyword(s):  
Surface Roughness ◽  
Silicon Wafer ◽  
Flow Rate ◽  
Silicon Wafers ◽  
Monocrystalline Silicon ◽  
Slurry Flow ◽  
Magnetorheological Finishing ◽  
Finishing Process ◽  
Process Factors ◽  
Slurry Flow Rate

In the present work, a novel hybrid finishing process that combines the two preferred methods in industries, namely, chemical-mechanical polishing (CMP) and magneto-rheological finishing (MRF), has been used to polish monocrystalline silicon wafers. The experiments were carried out on an indigenously developed double-disc chemical assisted magnetorheological finishing (DDCAMRF) experimental setup. The central composite design (CCD) was used to plan the experiments in order to estimate the effect of various process factors, namely polishing speed, slurry flow rate, percentage CIP concentration, and working gap on the surface roughness ([Formula: see text]) by DDCAMRF process. The analysis of variance was carried out to determine and analyze the contribution of significant factors affecting the surface roughness of polished silicon wafer. The statistical investigation revealed that percentage CIP concentration with a contribution of 30.6% has the maximum influence on the process performance followed by working gap (21.4%), slurry flow rate (14.4%), and polishing speed (1.65%). The surface roughness of polished silicon wafers was measured by the 3 D optical profilometer. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) were carried out to understand the surface morphology of polished silicon wafer. It was found that the surface roughness of silicon wafer improved with the increase in polishing speed and slurry flow rate, whereas it was deteriorated with the increase in percentage CIP concentration and working gap.

Gettering of iron impurities in p/p+ epitaxial silicon wafers with heavily boron‐doped substrates

1995 ◽  
Vol 66 (20) ◽  
pp. 2709-2711 ◽  
Author(s):  
Masaki Aoki ◽  
Toru Itakura ◽  
Nobuo Sasaki
Keyword(s):  
Silicon Wafers ◽  
Epitaxial Silicon ◽  
Boron Doped

A Precision Alignment Method to <100> Direction on (110) Silicon Wafer

2001 ◽  
Author(s):  
Fan-Gang Tseng ◽  
Kai-Chen Chang
Keyword(s):  
Silicon Wafer ◽  
Crystal Orientation ◽  
Silicon Wafers ◽  
Innovative Approach ◽  
Alignment Accuracy ◽  
Alignment Method

Abstract This paper proposes a novel pre-etch method to determine the lt;100gt; direction on (110) silicon wafers for bulk etching. Series of circular windows were arranged in an arc of radius 48.9 mm, and bulk-etched to form hexagonal shapes for crystal orientation finding. The corners of the hexagons can be used as an alignment reference for the indication of the lt;100gt; direction on (110) silicon wafers. This innovative approach has been demonstrated experimentally to give an orientation-alignment accuracy of ± 0.03° for (110) wafers with 4-inch diameter.

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