Gettering of iron impurities in p/p+ epitaxial silicon wafers with heavily boron‐doped substrates

1995 ◽  
Vol 66 (20) ◽  
pp. 2709-2711 ◽  
Author(s):  
Masaki Aoki ◽  
Toru Itakura ◽  
Nobuo Sasaki
Keyword(s):  
Silicon Wafers ◽  
Epitaxial Silicon ◽  
Boron Doped

Preparation of integrated circuits for TEM electromigration in situ studies

1986 ◽  
Vol 44 ◽  
pp. 882-883
Author(s):  
J. V. Maskowitz ◽  
W. E. Rhoden ◽  
D. R. Kitchen ◽  
R. E. Omlor ◽  
P. F. Lloyd
Keyword(s):  
Integrated Circuits ◽  
Crystallographic Orientation ◽  
Silicon Wafers ◽  
Minimum Size ◽  
Test Vehicle ◽  
In Situ Studies ◽  
Boron Doped ◽  
Doped Silicon ◽  
Drill Holes

The fabrication of the aluminum bridge test vehicle for use in the crystallographic studies of electromigration involves several photolithographic processes, some common, while others quite unique. It is most important to start with a clean wafer of known orientation. The wafers used are 7 mil thick boron doped silicon. The diameter of the wafer is 1.5 inches with a resistivity of 10-20 ohm-cm. The crystallographic orientation is (111).Initial attempts were made to both drill and laser holes in the silicon wafers then back fill with photoresist or mounting wax. A diamond tipped dentist burr was used to successfully drill holes in the wafer. This proved unacceptable in that the perimeter of the hole was cracked and chipped. Additionally, the minimum size hole realizable was > 300 μm. The drilled holes could not be arrayed on the wafer to any extent because the wafer would not stand up to the stress of multiple drilling.

Stability Study of Silicon Heterojunction Solar cells fabricated with Gallium‐ and Boron‐doped Silicon Wafers

Solar RRL ◽  
2021 ◽  
Author(s):  
Bruno Vicari Stefani ◽  
Moonyong Kim ◽  
Matthew Wright ◽  
Anastasia Soeriyadi ◽  
Dmitriy Andronikov ◽  
...  
Keyword(s):  
Solar Cells ◽  
Stability Study ◽  
Silicon Wafers ◽  
Heterojunction Solar Cells ◽  
Boron Doped ◽  
Doped Silicon ◽  
Silicon Heterojunction Solar Cells

Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

2018 ◽  
Vol 57 (4) ◽  
pp. 041301 ◽  
Author(s):  
Catherin Gemmel ◽  
Jan Hensen ◽  
Lasse David ◽  
Sarah Kajari-Schröder ◽  
Rolf Brendel
Keyword(s):  
Silicon Wafers ◽  
Process Window ◽  
Epitaxial Silicon ◽  
Carrier Lifetimes ◽  
Lift Off

Excellence of Gate Oxide Integrity in Metal-Oxide-Semiconductor Large-Scale-Integrated Circuits Based onP-/P-Thin-Film Epitaxial Silicon Wafers

1997 ◽  
Vol 36 (Part 1, No. 5A) ◽  
pp. 2565-2570 ◽  
Author(s):  
Hirofumi Shimizu ◽  
Yuji Sugino ◽  
Norio Suzuki ◽  
Shogo Kiyota ◽  
Koichi Nagasawa ◽  
...  
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Large Scale ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Silicon Wafers ◽  
Oxide Semiconductor ◽  
Epitaxial Silicon ◽  
Gate Oxide Integrity
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