Introduction to Logic Design Using Verilog HDL

Energy loss is a big challenge in digital logic design primarily due to impending end of Moore’s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17 % reduction in garbage lines, 92 % reduction in ancillary lines and 53 % reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design.

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Sequential Logic Design Using Verilog HDL

Verilog HDL Design Examples ◽

10.1201/b22315-3 ◽

2017 ◽

pp. 245-406

Author(s):

Joseph Cavanagh

Keyword(s):

Logic Design ◽

Verilog Hdl ◽

Sequential Logic

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The ASIC Design and Verification Based on Verilog HDL

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.433-440.4578 ◽

2012 ◽

Vol 433-440 ◽

pp. 4578-4583

Author(s):

Yu Ying Yuan ◽

Yong Gang Luo

Keyword(s):

Design Process ◽

Integrated Circuit ◽

Logic Design ◽

Verilog Hdl ◽

Asic Design ◽

Application Specific Integrated Circuit ◽

Design Requirements ◽

Cross Connect ◽

Application Specific ◽

Important Design

Logic design and verification is the frontend of ASIC (Application Specific Integrated Circuit), and is a very important design part during the design process of ASIC. A Verilog HDL design case－2×2 SDH digital cross-connect matrix is provided to illustrate the entire design process including logic-level description, verification and synthesis based on the frontend tools of Synopsys. After that a gate-level netlist conforming to the design requirements can be obtained.

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