Sequential Logic Design Using Verilog HDL

Verilog HDL Design Examples ◽

10.1201/b22315-3 ◽

2017 ◽

pp. 245-406

Author(s):

Joseph Cavanagh

Keyword(s):

Logic Design ◽

Verilog Hdl ◽

Sequential Logic

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Sequential Logic Design Using Verilog HDL

Digital Design and Verilog HDL Fundamentals ◽

10.1201/9781315218670-8 ◽

2017 ◽

pp. 739-820

Author(s):

Joseph Cavanagh

Keyword(s):

Logic Design ◽

Verilog Hdl ◽

Sequential Logic

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Sequential Logic Design

Unleash the System On Chip using FPGAs and Handel C ◽

10.1007/978-1-4020-9362-3_3 ◽

2009 ◽

pp. 43-59

Author(s):

Rajanish K. Kamat ◽

Santhosh A. Shinde ◽

Vinod G. Shelake

Keyword(s):

Logic Design ◽

Sequential Logic

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Sequential Logic Design

Digital Design and Computer Architecture ◽

10.1016/b978-0-12-820064-3.00003-9 ◽

2022 ◽

pp. 106-169

Author(s):

Sarah L. Harris ◽

David Harris

Keyword(s):

Logic Design ◽

Sequential Logic

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Sequential Logic Design

Introduction to Logic Circuits & Logic Design with VHDL ◽

10.1007/978-3-319-34195-8_7 ◽

2016 ◽

pp. 195-264

Author(s):

Brock J. LaMeres

Keyword(s):

Logic Design ◽

Sequential Logic

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Combinational Logic Design Using Verilog HDL

Verilog HDL Design Examples ◽

10.1201/b22315-2 ◽

2017 ◽

pp. 145-243

Author(s):

Joseph Cavanagh

Keyword(s):

Logic Design ◽

Combinational Logic ◽

Verilog Hdl

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Sequential Logic Design

Introduction to Logic Circuits & Logic Design with Verilog ◽

10.1007/978-3-319-53883-9_7 ◽

2017 ◽

pp. 199-270

Author(s):

Brock J. LaMeres

Keyword(s):

Logic Design ◽

Sequential Logic

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Combinational Logic Design Using Verilog HDL

Digital Design and Verilog HDL Fundamentals ◽

10.1201/9781315218670-4 ◽

2017 ◽

pp. 231-423

Author(s):

Joseph Cavanagh

Keyword(s):

Logic Design ◽

Combinational Logic ◽

Verilog Hdl

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Sequential Logic Design

Fundamentals of Digital Logic and Microcomputer Design ◽

10.1002/0471733520.ch5 ◽

2005 ◽

pp. 135-184

Keyword(s):

Logic Design ◽

Sequential Logic

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Describing Combinational and Sequential Logic using Verilog HDL

FSM-Based Digital Design Using Verilog HDL ◽

10.1002/9780470987629.ch8 ◽

2008 ◽

pp. 197-265

Keyword(s):

Verilog Hdl ◽

Sequential Logic

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High functionality reversible arithmetic logic unit

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v10i3.pp2329-2335 ◽

2020 ◽

Vol 10 (3) ◽

pp. 2329

Author(s):

Shaveta Thakral ◽

Dipali Bansal

Keyword(s):

Power Dissipation ◽

Logic Gates ◽

Reversible Logic ◽

Logic Design ◽

Quantum Cost ◽

Verilog Hdl ◽

Power Efficient ◽

Reversible Logic Gates ◽

Reversible Alu ◽

Logic Unit

Energy loss is a big challenge in digital logic design primarily due to impending end of Moore’s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17 % reduction in garbage lines, 92 % reduction in ancillary lines and 53 % reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design.

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