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ESD Protection Circuits Using NMOS Parasitic Bipolar Transistor
Electrostatic Discharge Protection
◽
10.1201/b18976-8
◽
2017
◽
pp. 141-162
Author(s):
Teruo Suzuki
Keyword(s):
Bipolar Transistor
◽
Esd Protection
◽
Protection Circuits
◽
Parasitic Bipolar Transistor
Download Full-text
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Cited By
References
Investigations of using NMOS parasitic bipolar transistor for ESD protection circuits
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)
◽
10.1109/icsict.2018.8565810
◽
2018
◽
Author(s):
Teruo Suzuki
Keyword(s):
Bipolar Transistor
◽
Esd Protection
◽
Protection Circuits
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Parasitic Bipolar Transistor
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Investigation of parasitic bipolar transistor in rail-based electrostatic discharge (ESD) protection circuits
IEICE Electronics Express
◽
10.1587/elex.16.20190306
◽
2019
◽
Vol 16
(18)
◽
pp. 20190306-20190306
Author(s):
Pengyu Lai
◽
Xianrui Li
◽
Hui Wang
◽
Zhong Chen
Keyword(s):
Electrostatic Discharge
◽
Bipolar Transistor
◽
Esd Protection
◽
Protection Circuits
◽
Parasitic Bipolar Transistor
Download Full-text
On a Parasitic Bipolar Transistor Action in a Diode ESD Protection Device
Circuits and Systems
◽
10.4236/cs.2016.79199
◽
2016
◽
Vol 07
(09)
◽
pp. 2286-2295
Author(s):
Jin Young Choi
Keyword(s):
Bipolar Transistor
◽
Protection Device
◽
Esd Protection
◽
Parasitic Bipolar Transistor
Download Full-text
Using device simulations to optimize ESD protection circuits
2004 International Symposium on Electromagnetic Compatibility (IEEE Cat. No.04CH37559)
◽
10.1109/isemc.2004.1349956
◽
2004
◽
Cited By ~ 6
Author(s):
B. Fankhauser
◽
B. Deutschmann
Keyword(s):
Esd Protection
◽
Protection Circuits
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Design of Gate-Ground-NMOS-Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn-On
ETRI Journal
◽
10.4218/etrij.09.1209.0045
◽
2009
◽
Vol 31
(6)
◽
pp. 725-731
◽
Cited By ~ 4
Author(s):
Yong-Seo Koo
◽
Kwangsoo Kim
◽
Shihong Park
◽
Kwidong Kim
◽
Jong-Kee Kwon
Keyword(s):
Leakage Current
◽
Turn On
◽
Low Leakage
◽
Low Leakage Current
◽
Esd Protection
◽
Protection Circuits
Download Full-text
Analysis and compact modeling of a vertical grounded-base NPN bipolar transistor used as an ESD protection in a smart power technology
Proceedings of the 2000 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.00CH37124)
◽
10.1109/bipol.2000.886167
◽
2002
◽
Cited By ~ 2
Author(s):
G. Bertrand
◽
C. Delage
◽
M. Bafleur
◽
N. Nolhier
◽
J.M. Dorkel
◽
...
Keyword(s):
Bipolar Transistor
◽
Compact Modeling
◽
Smart Power
◽
Esd Protection
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A new I/O signal latchup phenomenon in voltage tolerant ESD protection circuits
2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.
◽
10.1109/relphy.2003.1197725
◽
2003
◽
Cited By ~ 7
Author(s):
J. Salcedo-Suner
◽
R. Cline
◽
C. Duvvury
◽
A. Cadena-Hernandez
◽
L. Ting
◽
...
Keyword(s):
Esd Protection
◽
Protection Circuits
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New design concept for on-chip ESD protection circuits with already-on device in nanoscale CMOS technology
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.
◽
10.1109/apccas.2004.1413010
◽
2005
◽
Author(s):
Ming-Dou Ker
◽
Kuo-Chun Hsu
Keyword(s):
Cmos Technology
◽
Design Concept
◽
Nanoscale Cmos
◽
Esd Protection
◽
Protection Circuits
◽
On Chip
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A physics-based compact model for SCR devices used in ESD protection circuits
2013 IEEE International Reliability Physics Symposium (IRPS)
◽
10.1109/irps.2013.6531947
◽
2013
◽
Cited By ~ 10
Author(s):
R. Mertens
◽
E. Rosenbaum
Keyword(s):
Compact Model
◽
Esd Protection
◽
Protection Circuits
Download Full-text
Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits
2013 IEEE 10th International Conference on ASIC
◽
10.1109/asicon.2013.6811960
◽
2013
◽
Author(s):
Guangyi Lu
◽
Yuan Wang
◽
Jian Cao
◽
Song Jia
◽
Ganggang Zhang
◽
...
Keyword(s):
Gate Voltage
◽
Voltage Bias
◽
Esd Protection
◽
Protection Circuits
Download Full-text
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