Metal-Semiconductor Field-Effect Transistors and Integrated Circuits Based on ZnO and Related Oxides

2012 ◽  
pp. 369-434
Author(s):  
Heiko Frenzel ◽  
Michael Lorenz ◽  
Friedrich-L. Schein ◽  
Alexander Lajn ◽  
Fabian J. Klüpfel ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistors

scholarly journals Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 454
Author(s):  
You Wang ◽  
Yu Mao ◽  
Qizheng Ji ◽  
Ming Yang ◽  
Zhaonian Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Field Effect ◽  
Electrostatic Discharge ◽  
Field Effect Transistors ◽  
Test Method ◽  
Current Path ◽  
Simulation Results ◽  
Current Characteristics ◽  
Aided Design

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

Progress in SiC nanowire field-effect-transistors for integrated circuits and sensing applications

2022 ◽  
pp. 111704
Author(s):  
Konstantinos Zekentes ◽  
Jihoon Choi ◽  
Valérie Stambouli ◽  
Edwige Bano ◽  
Olfa Karker ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Sensing Applications

Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application

2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Logic Synthesis ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Timing Models ◽  
High Temperature Operation

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

Gate Current Modeling for Insulating Gate III-N Heterostructure Field-Effect Transistors

2002 ◽  
Vol 743 ◽  
Author(s):  
Frederick W. Clarke ◽  
Fat Duen Ho ◽  
M. Asif Khan ◽  
Grigory Simin ◽  
J. Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Elevated Temperatures ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Wide Band ◽  
Gate Leakage ◽  
Gate Current ◽  
Heterostructure Field Effect Transistors ◽  
Voltage Swing

AbstractGate current plays an important role in determining the characteristics and limiting performance of GaN-based field effect transistors. In GaN-based HFETs, the gate current limits the gate voltage swing and, hence, the maximum device current. Since the electron transport across the wide band gap barrier layer involves trapping, under certain bias conditions, the gate current leads to the threshold voltage shifts and causes reliability problems. Under reverse bias, the gate leakage in GaN-based HFET dominates the minimum (pinch-off) drain current. Insulating gate HFETs (i.e. Metal Oxide Heterostructure Field Effect Transistors – MOSHFETs) have the gate leakage currents 4 – 6 orders of magnitude lower than HFETs, even at elevated temperatures up to 300 °C. In this paper, we report on the gate current characteristics in these devices at room and elevated temperatures. We propose a semi-empirical model for the current-voltage characteristics in these devices, which is in good agreement with experimental data. Our data also show that both tunneling and temperature activation are important factors in MOSHFETs. These results are important for possible applications of GaN MOSHFETs in high power amplifiers and power switches as well as in non-volatile memory devices and integrated circuits that will operate in a much wider temperature range than conventional silicon and GaAs devices.

High mobility top gated field-effect transistors and integrated circuits based on chemical vapor deposition-derived monolayer MoS2

2016 ◽  
Vol 6 (2) ◽  
pp. 198-204 ◽  
Author(s):  
Dianzhong Wu ◽  
Zhiyong Zhang ◽  
Danhui Lv ◽  
Guoli Yin ◽  
Zhijian Peng ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Integrated Circuits ◽  
Vapor Deposition ◽  
Field Effect ◽  
Field Effect Transistors ◽  
High Mobility ◽  
Chemical Vapor
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