High-k Dielectrics and Metal Gate Electrodes on SOI MuGFETs

2012 ◽  
pp. 75-166
2012 ◽  
Vol 187 ◽  
pp. 57-60 ◽  
Author(s):  
Guang Yaw Hwang ◽  
J.H. Liao ◽  
S.F. Tzou ◽  
Mark Lin ◽  
Autumn Yeh ◽  
...  

Beginning at the 45nm node, the semiconductor industry is moving to high-k gate dielectrics and metal gate electrodes for CMOS logic devices [. Although different approaches of building these devices are being pursued, most of the industry has consolidated behind a gate last approach, in which the transistor is built around a dummy poly polysilicon gate, which is subsequently removed and replaced with a metal gate. Current approaches to removing the dummy poly gate include plasma-based dry processes and liquid-phase wet etching.


2009 ◽  
Vol 145-146 ◽  
pp. 215-218
Author(s):  
Masayuki Wada ◽  
Sylvain Garaud ◽  
I. Ferain ◽  
Nadine Collaert ◽  
Kenichi Sano ◽  
...  

High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.


2002 ◽  
Author(s):  
Jacob C. Hooker ◽  
Robert J. P. Lander ◽  
Z. M. Rittersma ◽  
Tom Schram ◽  
Guilherme S. Lujan ◽  
...  

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