MOS Gate Circuits

2018 ◽  
pp. 163-199
Author(s):  
John E. Ayers
Keyword(s):  
1985 ◽  
Vol 21 (1) ◽  
pp. 16-17 ◽  
Author(s):  
M. Garrigues ◽  
A. Pavlin
Keyword(s):  

2006 ◽  
Vol 527-529 ◽  
pp. 1261-1264 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Sumi Krishnaswami ◽  
Brett A. Hull ◽  
Bradley Heath ◽  
Mrinal K. Das ◽  
...  

8 mΩ-cm2, 1.8 kV power DMOSFETs in 4H-SiC are presented in this paper. A 0.5 μm long MOS gate length was used to minimize the MOS channel resistance. The DMOSFETs were able to block 1.8 kV with the gate shorted to the source. At room temperature, a specific onresistance of 8 mΩ-cm2 was measured with a gate bias of 15 V. At 150 oC, the specific onresistance increased to 9.6 mΩ-cm2. The increase in drift layer resistance due to a decrease in bulk electron mobility was partly cancelled out by the negative shift in MOS threshold voltage at elevated temperatures. The device demonstrated extremely fast, low loss switching characteristics. A significant improvement in converter efficiency was observed when the 4H-SiC DMOSFET was used instead of an 800 V silicon superjunction MOSFET in a simple boost converter configuration.


2016 ◽  
Vol 37 (2) ◽  
pp. 205-208 ◽  
Author(s):  
Wanjun Chen ◽  
Chao Liu ◽  
Xuefeng Tang ◽  
Lunfei Lou ◽  
Wu Cheng ◽  
...  
Keyword(s):  
Turn On ◽  

1981 ◽  
Vol 4 ◽  
Author(s):  
C J Pollard ◽  
A E Glaccum ◽  
J D Speight

ABSTRACTThe optimum e-beam anneal conditions for damage free wafer annealing, implant activation uniformity across 3 inch wafers and low dose boron activation have been investigated with reference to the needs of MOS device processing. Some effects of e-beam annealing on MOS gate dielectrics are reported.


Author(s):  
G. Brezeanu ◽  
C. Boianceanu ◽  
M. Brezeanu ◽  
Andrej Mihaila ◽  
F. Udrea ◽  
...  
Keyword(s):  

1999 ◽  
Vol 567 ◽  
Author(s):  
Udo Schwalke ◽  
Christian Gruensfelder ◽  
Alexander Gschwandtner ◽  
Gudrun Innertsberger ◽  
Martin Kerber

ABSTRACTWe have realized direct-tunneling gate oxide (1.6nm) NMOS and PMOS transistors by means of through-the-gate-implantation in a comer parasitics-free shallow-trench-isolation CMOS technology. In order to take full advantage of in-situ cluster-tool processing and to preserve initial wafer-surface quality, the essential part of the MOS gate is fabricated prior to device isolation and through-the-gate-implantation is utilized for well- and channel doping. In addition, a fully-reinforced-gate-oxide-perimeter is provided and trench comer parasitics are eliminated by the advanced process architecture EXTIGATE without increasing process complexity.


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