Optimised Multi-Scan H-Beam Annealing Of Mos Devices

1981 ◽  
Vol 4 ◽  
Author(s):  
C J Pollard ◽  
A E Glaccum ◽  
J D Speight
Keyword(s):  
Low Dose ◽  
Gate Dielectrics ◽  
Mos Devices ◽  
Device Processing ◽  
H Beam ◽  
Mos Gate ◽  
Mos Device

ABSTRACTThe optimum e-beam anneal conditions for damage free wafer annealing, implant activation uniformity across 3 inch wafers and low dose boron activation have been investigated with reference to the needs of MOS device processing. Some effects of e-beam annealing on MOS gate dielectrics are reported.

Integration of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications

2007 ◽  
Vol 84 (12) ◽  
pp. 2916-2920 ◽  
Author(s):  
Chang-Ta Yang ◽  
Kuei-Shu Chang-Liao ◽  
Hsin-Chun Chang ◽  
B.S. Sahu ◽  
Tzu-Chen Wang ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Metal Gate ◽  
Device Applications ◽  
Mos Device

Influences of MOS Device Characteristic under Different Oxygen-Dose Participations in the Silicon Substrate

2015 ◽  
Vol 656-657 ◽  
pp. 8-13
Author(s):  
Shen Li Chen ◽  
Tsung Shiung Lee ◽  
Yu Ting Huang
Keyword(s):  
Silicon Substrate ◽  
Czochralski Method ◽  
Silicon Substrates ◽  
Trap Charge ◽  
Substrate Quality ◽  
Mos Devices ◽  
Starting Point ◽  
Charge Characteristic ◽  
Mos Device

A silicon substrate is the starting point of producing the semiconductor component, so that the quality of semiconductor substrate is very important during the VLSI fabrication. In this paper, we will evaluate the influence of MOS device characteristics under different oxygen impurities in silicon substrates. In the course of silicon substrate pulling process by Czochralski method, the defect and impurity will be existed; the oxygen atom will be induced substrate dislocations and affected the substrate quality. In this work, different oxygen doses will be used in wafer to study the impacts on MOS CV curve characteristic, interface trap charge characteristic, ID-VDScurve, ID-VGScurve, and threshold voltage behaviors of MOS devices.

Al(ON) gate dielectrics for 4H-SiC MOS devices

2020 ◽  
Vol 532 ◽  
pp. 125434
Author(s):  
Jinghua Xia ◽  
Shihai Wang ◽  
Lixin Tian ◽  
Wenting Zhang ◽  
Hengyu Xu ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Mos Devices

Ellipsometric and XPS Studies of 4H-SiC/SiO2 Interfaces, and Sacrificial Oxide Stripped 4H-SiC Surfaces

2006 ◽  
Vol 527-529 ◽  
pp. 1027-1030 ◽  
Author(s):  
Owen J. Guy ◽  
L. Chen ◽  
G. Pope ◽  
K.S. Teng ◽  
T. Maffeis ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Interfacial Layer ◽  
Oxidation Process ◽  
Silicon Layer ◽  
Subsequent Removal ◽  
X Ray ◽  
Mos Devices ◽  
Device Processing ◽  
Form Features ◽  
Silicon Oxygen

The investigation of the silicon carbide surface after a sacrificial silicon oxidation technique is reported. Oxidation of SiC is a necessary step in the fabrication of MOS devices and device termination features such as field plates. Device processing requires the etching of windows through the oxide layer to form features such as metal / SiC contacts. However, this work indicates that a thin interfacial Si-O-C layer is still present after etching the oxide with hydrofluric acid (HF). Ellipsometry and X-ray photoelectron spectroscopy (XPS) have been used to evaluate this interfacial layer formed after oxide growth and after subsequent removal of oxide layers. An XPS analysis of the surface after removal of the oxide revealed that silicon, oxygen and carbon were all present in the remaining layer, which could not be removed by annealing at temperatures up to 1000°C. The Si-O-C layer could be eliminated by altering the oxidation conditions or by using a sacrificial silicon layer oxidation process. Ni Schottky barrier diodes fabricated on the 4H-SiC surface after removal of the oxide, displayed slightly higher ideality factors than those of diodes fabricated on untreated 4H-SiC samples.

Effect of Interfacial Localization of Phosphorus on Electrical Properties and Reliability of 4H-SiC MOS Devices

2013 ◽  
Vol 740-742 ◽  
pp. 695-698 ◽  
Author(s):  
Tsuyoshi Akagi ◽  
Hiroshi Yano ◽  
Tomoaki Hatayama ◽  
Takashi Fuyuki
Keyword(s):  
Interface State ◽  
State Density ◽  
Oxide Semiconductor ◽  
Conduction Band Edge ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Device Properties ◽  
Phosphorus Doped ◽  
Post Deposition ◽  
Mos Device

Metal-oxide-semiconductor (MOS) capacitors with phosphorus localized near the SiO2/SiC interface were fabricated on 4H-SiC by direct POCl3treatment followed by SiO2deposition. Post-deposition annealing (PDA) temperature affected MOS device properties and phosphorus distribution in the oxide. The sample with PDA at 800 °C showed narrow phosphorus-doped oxide region, resulting in low interface state density near the conduction band edge and small flatband voltage shift after FN injection. The interfacial localization of phosphorus improved both interface properties and reliability of 4H-SiC MOS devices.

A semi-empirical model for electron mobility at the SiC/SiO2 interface

2002 ◽  
Vol 742 ◽  
Author(s):  
Nelson S. Saks
Keyword(s):  
Surface Roughness ◽  
Empirical Model ◽  
Gate Voltage ◽  
Mobility Model ◽  
Coulomb Scattering ◽  
Mos Devices ◽  
Surface Roughness Scattering ◽  
Hall Effect Measurements ◽  
Semi Empirical ◽  
Mos Device

ABSTRACTThe mobility of electrons in inversion layers at SiC/SiO2 interfaces μinv has been characterized in 4H- and 6H-SiC using Hall effect measurements. In order to understand the cause of the low mobilities typically observed in SiC MOS devices, a semi-empirical mobility model has been developed based on a previous model for silicon inversion layers. Using this model, two scattering mechanisms, surface phonon and Coulomb scattering from high densities of electrons trapped at the SiC/SiO2 interface, are found to account reasonably well for the behavior of the mobility. The model employs a changing density of trapped electrons as a function of gate voltage to accurately model Coulomb scattering. Surprisingly, evidence of surface roughness scattering is not observed in any SiC MOS device.

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