Accurate Logic-Level Current Estimation for Digital CMOS Circuits

2006 ◽  
Vol 2 (1) ◽  
pp. 87-94
Author(s):  
P. Ruiz-de-Clavijo ◽  
J. Juan-Chico ◽  
M. J. Bellido ◽  
A. Millán ◽  
D. Guerrero ◽  
...  
Keyword(s):  
Cmos Circuits ◽  
Digital Cmos ◽  
Current Estimation ◽  
Logic Level

scholarly journals Logic-Level Fast Current Simulation for Digital CMOS Circuits

2005 ◽  
pp. 425-435 ◽  
Author(s):  
Paulino Ruiz de Clavijo ◽  
Jorge Juan-Chico ◽  
Manuel Jesús Bellido Díaz ◽  
Alejandro Millán Calderón ◽  
David Guerrero Martos ◽  
...  
Keyword(s):  
Cmos Circuits ◽  
Digital Cmos ◽  
Logic Level

scholarly journals Resonance circuits for adiabatic circuits

2003 ◽  
Vol 1 ◽  
pp. 223-228
Author(s):  
C. Schlachta ◽  
M. Glesner
Keyword(s):  
Energy Storage ◽  
Power Consumption ◽  
Charge Transport ◽  
Cmos Circuits ◽  
Digital Cmos ◽  
Storage Element

Abstract. One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

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