Fabrication of Poly-Silicon Nano-Wire Transistors on Plastic Substrates

2007 ◽  
Vol 7 (11) ◽  
pp. 4150-4153 ◽  
Author(s):  
ChangMin Park ◽  
SeHan Lee ◽  
MinSu Choi ◽  
MyungGil Kang ◽  
YoungChai Jung ◽  
...  

We report the fabrication and characterization of poly-Si nanowire transistors on flexible substrates. The nanowire transistors are fabricated on a SiO2/Si substrate using conventional CMOS processes, and then they are transferred onto polyimide substrates. The transfer process is performed by spin-coating of polyimide, curing (annealing) of the polyimide layer, and removal of the SiO2 sacrificial layer. The optimized curing condition results in the maximum bending of 150° with full recovery. The nanowire transistors exhibit transistor characteristics as a function of the backgate bias. Our new process can be applied to the fabrication of Si-nanowire transistors with larger mobilities.

2007 ◽  
Vol 7 (11) ◽  
pp. 4150-4153
Author(s):  
ChangMin Park ◽  
SeHan Lee ◽  
MinSu Choi ◽  
MyungGil Kang ◽  
YoungChai Jung ◽  
...  

We report the fabrication and characterization of poly-Si nanowire transistors on flexible substrates. The nanowire transistors are fabricated on a SiO2/Si substrate using conventional CMOS processes, and then they are transferred onto polyimide substrates. The transfer process is performed by spin-coating of polyimide, curing (annealing) of the polyimide layer, and removal of the SiO2 sacrificial layer. The optimized curing condition results in the maximum bending of 150° with full recovery. The nanowire transistors exhibit transistor characteristics as a function of the backgate bias. Our new process can be applied to the fabrication of Si-nanowire transistors with larger mobilities.


2006 ◽  
Vol 53 (10) ◽  
pp. 2471-2477 ◽  
Author(s):  
Horng-Chih Lin ◽  
Ming-Hsien Lee ◽  
Chun-Jung Su ◽  
Shih-Wen Shen

2009 ◽  
Vol 55 (1) ◽  
pp. 28-31 ◽  
Author(s):  
Seung-Yong Lee ◽  
Chan-Oh Jang ◽  
Jung-Hwan Hyung ◽  
Dong-Joo Kim ◽  
Tae-Hong Kim ◽  
...  

2010 ◽  
Vol 87 (11) ◽  
pp. 2097-2102 ◽  
Author(s):  
Seungju Chun ◽  
Kang-Soo Han ◽  
Ju-Hyeon Shin ◽  
Heon Lee ◽  
Donghwan Kim

2017 ◽  
Vol 31 (33) ◽  
pp. 1750313
Author(s):  
A. Mahyuddin ◽  
A. Azrina ◽  
M. Z. Mohd Yusoff ◽  
Z. Hassan

An experimental investigation was conducted to explore the effect of inserting a single AlGaN interlayer between AlN epilayer and GaN/AlN heterostructures on Si (111) grown by molecular beam epitaxy (MBE). It is confirmed from the scanning electron microscopy (SEM) that the AlGaN interlayer has a remarkable effect on reducing the tensile stress and dislocation density in AlN top layer. Capacitance–voltage (C–V) measurements were conducted to study the electrical properties of AlN/GaN heterostructures. While deriving the findings through the calculation it is suggested that the AlGaN interlayer can significantly reduce the value of effective oxide charge density and total effective number of charges per unit area which are [Formula: see text] and [Formula: see text], respectively.


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