scholarly journals Multi-Layer 2 Mil Line Technology

1981 ◽  
Vol 8 (1-2) ◽  
pp. 91-98
Author(s):  
Tamio Saito ◽  
Yoshikatsu Fukumoto
Keyword(s):  
Transmission Lines ◽  
High Speed ◽  
Signal Propagation ◽  
Propagation Delay ◽  
New Method ◽  
Technology Research ◽  
Silicon Chips ◽  
Layer 2 ◽  
Line Technology ◽  
Very High

Multi-layer 2 mil line technology has been increasingly required for VLSI and very high speed logic devices. This technology makes it possible to shorten the length of interconnection lines between VLSI silicon chips. Thus the signal propagation delay on the transmission lines can be minimized.Multi-layer 2 mil line technology research history, the new method and usages are discussed in this paper.

A LOW POWER AND VARIATION-INSENSITIVE CURRENT-MODE SIGNALING SCHEME

2013 ◽  
Vol 22 (08) ◽  
pp. 1350068
Author(s):  
XINSHENG WANG ◽  
YIZHE HU ◽  
LIANG HAN ◽  
JINGHU LI ◽  
CHENXU WANG ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Current Mode ◽  
Signal Propagation ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Noise Performance ◽  
On Chip ◽  
Variation Tolerance ◽  
Driving Signal

Process and supply variations all have a large influence on current-mode signaling (CMS) circuits, limiting their application on the fields of high-speed low power communication over long on-chip interconnects. A variation-insensitive CMS scheme (CMS-Bias) was offered, employing a particular bias circuit to compensate the effects of variations, and was robust enough against inter-die and intra-die variations. In this paper, we studied in detail the principle of variation tolerance of the CMS circuit and proposed a more suitable bias circuit for it. The CMS-Bias with the proposed bias circuit (CMS-Proposed) can acquire the same variation tolerance but consume less energy, compared with CMS-Bias with the original bias circuit (CMS-Original). Both the CMS schemes were fabricated in 180 nm CMOS technology. Simulation and measured results indicate that the two CMS interconnect circuits have the similar signal propagation delay when driving signal over a 10 mm line, but the CMS-Proposed offers about 9% reduction in energy/bit and 7.2% reduction in energy-delay-product (EDP) over the CMS-Original. Simulation results show that the two CMS schemes only change about 5% in delay when suffering intra-die variations, and have the same robustness against inter-die variations. Both simulation and measurements all show that the proposed bias circuits, employing self-biasing structure, contribute to robustness against supply variations to some extent. Jitter analysis presents the two CMS schemes have the same noise performance.

scholarly journals Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis

2013 ◽  
Vol 2 (1) ◽  
pp. 1
Author(s):  
T. Eudes ◽  
B. Ravelo ◽  
R. Al-Hayek
Keyword(s):  
Transfer Function ◽  
Transmission Lines ◽  
Time Domain ◽  
High Speed ◽  
Signal Integrity ◽  
Frequency Dispersion ◽  
Propagation Delay ◽  
High Rate ◽  
Propagation Time ◽  
Time Assessment

This paper presents an enlarged study about the 50-% propagation-time assessment of cascaded transmission lines (TLs). First and foremost, the accurate modeling and measurement technique of signal integrity (SI) for high-rate microelectronic interconnection is recalled. This model is based on the reduced transfer function extracted from the electromagnetic (EM) behavior of the interconnect line RLCG-parameters. So, the transfer function established takes into account both the frequency dispersion effects and the different propagation modes. In addition, the transfer function includes also the load and source impedance effects. Then, the SI analysis is proposed for high-speed digital signals through the developed model. To validate the model understudy, a prototype of microstrip interconnection with w = 500 µm and length d = 33 mm was designed, simulated, fabricated and tested. Then, comparisons between the frequency and time domain results from the model and from measurements are performed. As expected, good agreement between the S-parameters form measurements and the model proposed is obtained from DC to 8 GHz. Furthermore, a de-embedding method enabling to cancel out the connectors and the probe effects are also presented. In addition, an innovative time-domain characterization is proposed in order to validate the concept with a 2.38 Gbit/s-input data signal. Afterwards, the 50-% propagation-time assessment problem is clearly exposed. Consequently an extracting theory of this propagation-time with first order RC-circuits is presented. Finally, to show the relevance of this calculation, propagation-time simulations and an application to signal integrity issues are offered.

A Novel Approach to the Measurement and Characterization of Losses due to Surface Roughness in High Speed Transmission Lines

2011 ◽  
Vol 2011 (CICMT) ◽  
pp. 000241-000245
Author(s):  
Femi Akinwale ◽  
A. Ege Engin
Keyword(s):  
Surface Roughness ◽  
Transmission Lines ◽  
High Speed ◽  
Data Transfer ◽  
Signal Propagation ◽  
High Frequencies ◽  
Novel Approach ◽  
Critical Issues ◽  
5 Ghz

An accurate measurement technique is required to fully characterize the losses observed at high frequencies in transmission lines. Evaluation of losses seen at high frequencies is necessary to meet the high-speed data transfer rates that future applications will demand. Conductor properties and losses are two critical issues in signal path characterization. The nature of conductor losses is not well understood at high speeds. Classical models used for predicting the effects of surface roughness on signal propagation are known to breakdown around 5 GHz. Novel methods are sought to quantify the effects beyond 5 GHz. In this paper, a simple methodology to extract conductor loss is derived and validated based on a stripline configuration of two different widths. The proposed methodology is applicable to surface roughness loss characterization of both organic and ceramic packaging materials.

A Practical Method for Trace Exposure and Roughness Measurements and Implementation in High Speed Package Design

2012 ◽  
Author(s):  
Valentina Korchnoy ◽  
Jacov Brener
Keyword(s):  
Transmission Lines ◽  
Insertion Loss ◽  
High Frequency ◽  
High Speed ◽  
Transmission Loss ◽  
Signal Propagation ◽  
Practical Method ◽  
High Frequency Signal ◽  
Advantages And Disadvantages ◽  
Conductor Surface

Abstract High frequency signal propagation through transmission lines has been an important discipline for RF engineers. With advancements in digital technologies, especially when data rates reached multiple Gb/s, package designers have to consider parameters such as transmission loss and trace impedance in order to maintain signal integrity. For high frequency signals, the surface roughness of the copper trace becomes increasingly significant in determining conduction loss, due to current confinement to the conductor surface by the skin effect. Accurate 3D conductor surface maps are required for correct trace insertion loss simulation. Practical methods for package trace exposure and 3D surface height map acquisition are discussed in this paper. Advantages and disadvantages of these methods, and their implementation to real packages are shown. Using electrical parameters resulting from a 3D trace surface map, the error between electrical simulations and actual measurements of insertion loss in an FCBGA package have been reduced from 6% to nearly zero, enabling tighter margins in 10GB/s high speed serial design.

High-speed signal propagation on lossy transmission lines

1990 ◽  
Vol 34 (4) ◽  
pp. 601-615 ◽  
Author(s):  
A. Deutsch ◽  
G. V. Kopcsay ◽  
V. A. Ranieri ◽  
J. K. Cataldo ◽  
E. A. Galligan ◽  
...  
Keyword(s):  
Transmission Lines ◽  
High Speed ◽  
Signal Propagation ◽  
Lossy Transmission

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

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