High-speed signal propagation on lossy transmission lines

1990 ◽  
Vol 34 (4) ◽  
pp. 601-615 ◽  
Author(s):  
A. Deutsch ◽  
G. V. Kopcsay ◽  
V. A. Ranieri ◽  
J. K. Cataldo ◽  
E. A. Galligan ◽  
...  
Keyword(s):  
Transmission Lines ◽  
High Speed ◽  
Signal Propagation ◽  
Lossy Transmission

A Novel Approach to the Measurement and Characterization of Losses due to Surface Roughness in High Speed Transmission Lines

2011 ◽  
Vol 2011 (CICMT) ◽  
pp. 000241-000245
Author(s):  
Femi Akinwale ◽  
A. Ege Engin
Keyword(s):  
Surface Roughness ◽  
Transmission Lines ◽  
High Speed ◽  
Data Transfer ◽  
Signal Propagation ◽  
High Frequencies ◽  
Novel Approach ◽  
Critical Issues ◽  
5 Ghz

An accurate measurement technique is required to fully characterize the losses observed at high frequencies in transmission lines. Evaluation of losses seen at high frequencies is necessary to meet the high-speed data transfer rates that future applications will demand. Conductor properties and losses are two critical issues in signal path characterization. The nature of conductor losses is not well understood at high speeds. Classical models used for predicting the effects of surface roughness on signal propagation are known to breakdown around 5 GHz. Novel methods are sought to quantify the effects beyond 5 GHz. In this paper, a simple methodology to extract conductor loss is derived and validated based on a stripline configuration of two different widths. The proposed methodology is applicable to surface roughness loss characterization of both organic and ceramic packaging materials.

scholarly journals Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits

1992 ◽  
Vol 14 (4) ◽  
pp. 199-218 ◽  
Author(s):  
K. Z. Dimopoulos ◽  
J. N. Avaritsiotis ◽  
S. J. White
Keyword(s):  
Integrated Circuits ◽  
Transmission Lines ◽  
High Speed ◽  
Pulse Propagation ◽  
Unit Length ◽  
Coupled Line ◽  
Lossy Transmission ◽  
Electrical Modelling ◽  
High Bit Rates ◽  
On Chip

A method for the electrical parameters analysis and modelling of lossy-coupled multilayer on-chip interconnection lines at high bit rates is presented in detail. It can be used by the VLSI designer to analyze on-chip interconnections with linear, as well as nonlinear/time varying terminators and to simulate the pulse propagation characteristics in high-speed integrated circuits. First the capacitance, inductance, conductance and resistance matrices per unit length for the given multiconductor geometry is computed. A multiple coupled line model consisting of uncoupled lossy transmission lines and linear dependent current and voltage sources if finally calculated according to the capacitance, inductance, conductance and resistance matrix values computed.

A Practical Method for Trace Exposure and Roughness Measurements and Implementation in High Speed Package Design

2012 ◽  
Author(s):  
Valentina Korchnoy ◽  
Jacov Brener
Keyword(s):  
Transmission Lines ◽  
Insertion Loss ◽  
High Frequency ◽  
High Speed ◽  
Transmission Loss ◽  
Signal Propagation ◽  
Practical Method ◽  
High Frequency Signal ◽  
Advantages And Disadvantages ◽  
Conductor Surface

Abstract High frequency signal propagation through transmission lines has been an important discipline for RF engineers. With advancements in digital technologies, especially when data rates reached multiple Gb/s, package designers have to consider parameters such as transmission loss and trace impedance in order to maintain signal integrity. For high frequency signals, the surface roughness of the copper trace becomes increasingly significant in determining conduction loss, due to current confinement to the conductor surface by the skin effect. Accurate 3D conductor surface maps are required for correct trace insertion loss simulation. Practical methods for package trace exposure and 3D surface height map acquisition are discussed in this paper. Advantages and disadvantages of these methods, and their implementation to real packages are shown. Using electrical parameters resulting from a 3D trace surface map, the error between electrical simulations and actual measurements of insertion loss in an FCBGA package have been reduced from 6% to nearly zero, enabling tighter margins in 10GB/s high speed serial design.

scholarly journals Multi-Layer 2 Mil Line Technology

1981 ◽  
Vol 8 (1-2) ◽  
pp. 91-98
Author(s):  
Tamio Saito ◽  
Yoshikatsu Fukumoto
Keyword(s):  
Transmission Lines ◽  
High Speed ◽  
Signal Propagation ◽  
Propagation Delay ◽  
New Method ◽  
Technology Research ◽  
Silicon Chips ◽  
Layer 2 ◽  
Line Technology ◽  
Very High

Multi-layer 2 mil line technology has been increasingly required for VLSI and very high speed logic devices. This technology makes it possible to shorten the length of interconnection lines between VLSI silicon chips. Thus the signal propagation delay on the transmission lines can be minimized.Multi-layer 2 mil line technology research history, the new method and usages are discussed in this paper.

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