scholarly journals Computer Simulation of Hybrid Integrated Circuits Including Combined Electrical and Thermal Effects

1983 ◽  
Vol 10 (2-3) ◽  
pp. 171-176 ◽  
Author(s):  
Carl R. Zimmer
Keyword(s):  
Integrated Circuits ◽  
Thermal Effects ◽  
Thermal Environment ◽  
Variable Temperature ◽  
Three Dimensional ◽  
General Purpose ◽  
Voltage Source ◽  
Thermal Coupling ◽  
Analysis Programme ◽  
Environment Parameters

This paper describes the application of a modern general purpose network analysis programme SPICE2 for the electrothermal analysis of hybrid integrated circuits. Self thermal coupling effects are modelled using the non-linear dependent current and voltage source capability in this programme, together with thermal environment parameters obtained from a three-dimensional thermal analysis program. Although numerical results are given by a bipolar transistor, the method is also applicable to monolithic integrated circuits and to resistors with variable temperature coefficients as power dissipating elements.

Thermal Effects Due to Surface Films in Sliding Contact

1994 ◽  
Vol 116 (2) ◽  
pp. 238-245 ◽  
Author(s):  
Brian Vick ◽  
L. P. Golan ◽  
M. J. Furey
Keyword(s):  
Thermal Properties ◽  
Temperature Rise ◽  
Thermal Effects ◽  
Three Dimensional ◽  
Sliding Contact ◽  
Frictional Heat ◽  
Solution Technique ◽  
Surface Films ◽  
Thermal Coupling ◽  
Efficient Manner

The present work examines theoretically the influence of surface coatings on the temperatures produced by friction due to sliding contact. A generalized thermal model is developed which incorporates three-dimensional, transient heat transfer between layered media with thermal coupling at multiple, interacting contact patches. A solution technique based on a variation of the boundary element method is developed and utilized. The method allows for the solution of the distribution of frictional heat and the resulting temperature rise in an accurate yet numerically efficient manner. Results are presented showing the influence of film thickness, thermal properties, velocity, and contact area on the division of heat and surface temperature rise. The results show that a film with thermal properties different than those of the substrate can have a pronounced effect on the predicted temperature rise.

Investigation of Thermal Effects on Weapon System Components

1983 ◽  
Vol 105 (2) ◽  
pp. 227-231
Author(s):  
J. J. Labra
Keyword(s):  
Thermal Effects ◽  
Test Chamber ◽  
Three Dimensional ◽  
General Purpose ◽  
Structural Components ◽  
Design Changes ◽  
Environmental Test ◽  
Cause Of Failure ◽  
Computer Based ◽  
Complex Structural

A three-dimensional stress analysis of a 30-mm machine gun component on the Harrier Aircraft was conducted to investigate the cause of observed fractures. The analysis was made using a general purpose finite element computer program and a laboratory environmental test chamber. Based on this study, the probable cause of failure was identified and, as a result, the component manufacturer is considering possible design changes to alleviate this problem in further production. The study clearly demonstrates that computer-based technology can be successfully used in investigating causes of failure in complex structural components.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

scholarly journals Fabrication of Eutectic Ga-In Nanowire Arrays Based on Plateau–Rayleigh Instability

Molecules ◽  
2021 ◽  
Vol 26 (15) ◽  
pp. 4616
Author(s):  
Takashi Ikuno ◽  
Zen Somei
Keyword(s):  
Integrated Circuits ◽  
Substrate Surface ◽  
Three Dimensional ◽  
Average Diameter ◽  
Nanowire Arrays ◽  
Scanning Probe ◽  
Rayleigh Instability ◽  
Simple Method ◽  
Flat Substrate ◽  
Metal Nanowire

We have developed a simple method of fabricating liquid metal nanowire (NW) arrays of eutectic GaIn (EGaIn). When an EGaIn droplet anchored on a flat substrate is pulled perpendicular to the substrate surface at room temperature, an hourglass shaped EGaIn is formed. At the neck of the shape, based on the Plateau–Rayleigh instability, the EGaIn bridge with periodically varying thicknesses is formed. Finally, the bridge is broken down by additional pulling. Then, EGaIn NW is formed at the surface of the breakpoint. In addition, EGaIn NW arrays are found to be fabricated by pulling multiple EGaIn droplets on a substrate simultaneously. The average diameter of the obtained NW was approximately 0.6 μm and the length of the NW depended on the amount of droplet anchored on the substrate. The EGaIn NWs fabricated in this study may be used for three-dimensional wiring for integrated circuits, the tips of scanning probe microscopes, and field electron emission arrays.

scholarly journals High-Performance On-Chip Silicon Beamsplitter Based on Subwavelength Metamaterials for Enhanced Fabrication Tolerance

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1304
Author(s):  
Raquel Fernández de Cabo ◽  
David González-Andrade ◽  
Pavel Cheben ◽  
Aitor V. Velasco
Keyword(s):  
Integrated Circuits ◽  
Fundamental Mode ◽  
High Performance ◽  
Three Dimensional ◽  
High Sensitivity ◽  
Power Splitting ◽  
Excess Loss ◽  
Power Splitters ◽  
On Chip ◽  
Efficient Power

Efficient power splitting is a fundamental functionality in silicon photonic integrated circuits, but state-of-the-art power-division architectures are hampered by limited operational bandwidth, high sensitivity to fabrication errors or large footprints. In particular, traditional Y-junction power splitters suffer from fundamental mode losses due to limited fabrication resolution near the junction tip. In order to circumvent this limitation, we propose a new type of high-performance Y-junction power splitter that incorporates subwavelength metamaterials. Full three-dimensional simulations show a fundamental mode excess loss below 0.1 dB in an ultra-broad bandwidth of 300 nm (1400–1700 nm) when optimized for a fabrication resolution of 50 nm, and under 0.3 dB in a 350 nm extended bandwidth (1350–1700 nm) for a 100 nm resolution. Moreover, analysis of fabrication tolerances shows robust operation for the fundamental mode to etching errors up to ± 20 nm. A proof-of-concept device provides an initial validation of its operation principle, showing experimental excess losses lower than 0.2 dB in a 195 nm bandwidth for the best-case resolution scenario (i.e., 50 nm).

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