scholarly journals Hybrid Model: An Efficient Symmetric Multiprocessor Reference Model

2015 ◽  
Vol 2015 ◽  
pp. 1-10
Author(s):  
Shupeng Wang ◽  
Kai Huang ◽  
Tianyi Xie ◽  
Xiaolang Yan
Keyword(s):  
Hybrid Model ◽  
Reference Model ◽  
Cost Effective ◽  
Functional Verification ◽  
Simulation Based ◽  
Design Resources ◽  
Hardware Description ◽  
Description Languages ◽  
High Level ◽  
The Cost

Functional verification has become one of the main bottlenecks in the cost-effective design of embedded systems, particularly for symmetric multiprocessors. It is estimated that verification in its entirety accounts for up to 60% of design resources, including duration, computer resources, and total personnel. Simulation-based verification is a long-standing approach used to locate design errors in the symmetric multiprocessor verification. The greatest challenge of simulation-based verification is the creation of the reference model of the symmetric multiprocessor. In this paper, we propose an efficient symmetric multiprocessor reference model, Hybrid Model, written with SystemC. SystemC can provide a high-level simulation environment and is faster than the traditional hardware description languages. Hybrid Model has been implemented in an efficient 32-bit symmetric multiprocessor verification. Experimental results show our proposed model is a fast, accurate, and efficient symmetric multiprocessor reference model and it is able to help designers to locate design errors easily and accurately.

scholarly journals Functional Verification of Large-integers Circuits using a Cosimulation-based Approach

2017 ◽  
Vol 7 (4) ◽  
pp. 2192
Author(s):  
Nejmeddine Alimi ◽  
Younes Lahbib ◽  
Mohsen Machhout ◽  
Rached Tourki
Keyword(s):  
Good Evidence ◽  
Modular Arithmetic ◽  
Functional Verification ◽  
Hardware Description Languages ◽  
Abstraction Level ◽  
Hardware Description ◽  
Multi Level ◽  
Description Languages ◽  
High Level ◽  
Real Challenge

Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer’s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability.

Making E-Training Cost Effective through Quality Assurance

2009 ◽  
pp. 623-631
Author(s):  
Lichia Yiu ◽  
Raymond Saner
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
Web Based ◽  
Corporate Learning ◽  
Use Of Technology ◽  
Training Cost ◽  
E Learning ◽  
American Society ◽  
High Level ◽  
The Cost

Since the 1990s, more and more corporate learning has been moved online to allow for flexibility, just-in-time learning, and cost saving in delivering training. This trend has been evolved along with the introduction of Web-based applications for HRM purposes, known as electronic Human Resource Management (e-HRM). By 2005, 39.67% of the corporate learning, among the ASTD (American Society for Training and Development) benchmarking forum companies, was delivered online in comparison to 10.5% in 2001. E-learning has now reached “a high level of (technical) sophistication, both in terms of instructional development and the effective management of resources” in companies with high performance learning function (ASTD, 2006, p.4). The cost per unit, reported by ASTD in its 2006 State of Industry Report, has been declining since 2000 despite the higher training hours received per employee thanks to the use of technology based training delivery and its scalability. However, the overall quality of e-learning either public available in the market or implemented at the workplace remains unstable.

The Optimized Risk Management of the Waste From TENORM and Nuclear Industries: How to Harmonize Risk From Various Sources

2010 ◽  
Author(s):  
Yoko Fujikawa ◽  
Michikuni Shimo ◽  
Hironori Yonehara ◽  
Tadashi Tujimoto
Keyword(s):  
Risk Management ◽  
Cost Effectiveness ◽  
Cost Effective ◽  
Disposal Option ◽  
Disposal Options ◽  
High Level ◽  
The Cost ◽  
Disposal Cost ◽  
Underground Burial ◽  
The Ideal

We compared the existing regulation on management of radioactive and non-radioactive wastes with the ideal legislation procedures for protection of environment. The comparison revealed the necessity of risk-based regulation, consideration for ethics and cost-effectiveness of the regulation, and optimal usage of regulation resources. In order to assess the cost-effectiveness of several different waste disposal options, the concept of disposal cost per unit radiotoxicity (mSv or m3) in waste (CPR hereafter) was introduced and calculated. The results revealed that current disposal option of high level radioactive waste (underground burial) was more cost-effective than that of TENORM and asbestos containing waste.

Experiences with High-Level Design and Modelling of Digital Systems

1995 ◽  
Vol 32 (4) ◽  
pp. 333-340
Author(s):  
S. J. Sangwine
Keyword(s):  
Digital Systems ◽  
Hardware Description Languages ◽  
Transversal Filter ◽  
Hardware Description ◽  
Ieee Standard ◽  
Level Design ◽  
Description Languages ◽  
High Level ◽  
The University

Experiences with high-level design and modelling of digital systems Design and modelling of digital systems has been taught at the University of Reading for six years, using Silvar-Lisco HELIX and lately IEEE Standard VHDL hardware description languages. Three exercises have been used throughout this time. These are: modelling of a multiplier-accumulator, design and modelling of a transversal filter, and specification-level modelling of a FIFO.

Notification-Oriented Paradigm to Implement Digital Hardware

2018 ◽  
Vol 27 (08) ◽  
pp. 1850124 ◽  
Author(s):  
Ricardo Kerschbaumer ◽  
Robson R. Linhares ◽  
Jean M. Simão ◽  
Paulo C. Stadzisz ◽  
Carlos R. Erig Lima
Keyword(s):  
High Performance ◽  
Digital Circuits ◽  
Operating Frequency ◽  
Detailed Knowledge ◽  
Use Of Resources ◽  
Digital Hardware ◽  
Hardware Description ◽  
Description Languages ◽  
Circuit Description ◽  
High Level

The growing demand for high-performance digital circuits, mainly involving FPGAs, increases the demand for high-level synthesis (HLS) tools. Traditional Hardware Description Languages (HDLs) are complex and depend on low-level abstractions, thereby requiring hardware detailed knowledge from developers. In turn, the current HLS tools are based on proprietary or C/C[Formula: see text] derived languages, which allow easier circuit description but decrease performance. This work presents an alternative solution for designing digital circuits, which arises from the Notification-Oriented Paradigm (NOP). The NOP is an alternative computing solution based upon a set of predefined interconnected entities whose collaborations are performed through precise notifications. The NOP, when targeted to digital hardware (DH), allows the developer to describe the circuit behavior just by connecting and parameterizing elements. The result is a VHDL file that can be compiled for any platform from any manufacturer. In order to check the functionality of this approach, sorting circuits were built both with usual VHDL and with the NOP VHDL aiming to compare the resulting circuits in terms of operating frequency and resource use. The results show that the NOP VHDL approach facilitates the build of digital circuits when compared to the VHDL usual approach without limiting the operating frequency or increasing the use of resources.

Making E-Training Cost Effective through Quality Assurance

2011 ◽  
pp. 1413-1422
Author(s):  
Lichia Yiu ◽  
Raymond Saner
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
Web Based ◽  
Corporate Learning ◽  
Use Of Technology ◽  
Training Cost ◽  
E Learning ◽  
American Society ◽  
High Level ◽  
The Cost

Since the 1990s, more and more corporate learning has been moved online to allow for flexibility, just-in-time learning, and cost saving in delivering training. This trend has been evolved along with the introduction of Web-based applications for HRM purposes, known as electronic Human Resource Management (e-HRM). By 2005, 39.67% of the corporate learning, among the ASTD (American Society for Training and Development) benchmarking forum companies, was delivered online in comparison to 10.5% in 2001. E-learning has now reached “a high level of (technical) sophistication, both in terms of instructional development and the effective management of resources” in companies with high performance learning function (ASTD, 2006, p.4). The cost per unit, reported by ASTD in its 2006 State of Industry Report, has been declining since 2000 despite the higher training hours received per employee thanks to the use of technology based training delivery and its scalability. However, the overall quality of e-learning either public available in the market or implemented at the workplace remains unstable.

scholarly journals Dynamic Hardware Development

2008 ◽  
Vol 2008 ◽  
pp. 1-10 ◽  
Author(s):  
Stephen Craven ◽  
Peter Athanas
Keyword(s):  
Digital Design ◽  
Development Environment ◽  
Dynamically Reconfigurable ◽  
Reconfigurable Design ◽  
Synthesis Tool ◽  
Embedded Controller ◽  
Hardware Description ◽  
Description Languages ◽  
High Level ◽  
Tools And Techniques

Applications that leverage the dynamic partial reconfigurability of modern FPGAs are few, owing in large part to the lack of suitable tools and techniques to create them. While the trend in digital design is towards higher levels of design abstractions, forgoing hardware description languages in some cases for high-level languages, the development of a reconfigurable design requires developers to work at a low level and contend with many poorly documented architecture-specific aspects. This paper discusses the creation of a high-level development environment for reconfigurable designs that leverage an existing high-level synthesis tool to enable the design, simulation, and implementation of dynamically reconfigurable hardware solely from a specification written in C. Unlike previous attempts, this approach encompasses the entirety of design and implementation, enables self-re-configuration through an embedded controller, and inherently handles partial reconfiguration. Benchmarking numbers are provided, which validate the productivity enhancements this approach provides.

Development and Evaluation of an Electronic Drug and Therapeutics Bulletin

2002 ◽  
Vol 36 (10) ◽  
pp. 1637-1641 ◽  
Author(s):  
Christopher P Alderman
Keyword(s):  
Electronic Mail ◽  
Cost Effective ◽  
Extensive Literature ◽  
Therapeutics Bulletin ◽  
Level Of Satisfaction ◽  
The Us ◽  
High Level ◽  
Effective Use ◽  
The Cost ◽  
E Mail

OBJECTIVE: To describe the development, implementation, and initial evaluation of a paperless drug and therapeutics bulletin that is distributed by electronic mail from the pharmacy department of an Australian teaching hospital. OUTCOMES: A standardized format for the bulletin was designed and approved in February 2001. The aim of the bulletin is to facilitate the timely dissemination of concise, factual information about issues of current interest in therapeutics, drug safety, and the cost-effective use of medicines. A simple and attractive graphic design was chosen, and the hospital's clinical pharmacists and drug information staff developed an initial bank of content during the period immediately preceding the launch. The bulletin is presented as a 1-page, read-only file in Word for Windows format and was initially distributed by electronic mail to all users of the hospital's computerized communication network. As the popularity of the bulletin increased, healthcare practitioners from outside of the hospital began to request permission for inclusion on the circulation list, and the content was frequently forwarded by E-mail to workers in other hospitals and community-based settings. The bulletin is now distributed to pharmacists around Australia via 2 separate moderated discussion lists, one of which provides an archive site for previous editions. Healthcare workers in Singapore, the US, Canada, and New Zealand also receive the bulletin, which is now also abstracted by a major Australian pharmacy journal. A readership survey (also electronically distributed) was used to seek feedback after the publication of the first 12 editions. Readers indicated a high level of satisfaction with the content, format, and frequency of distribution of the materials. CONCLUSIONS: Although the concept and execution of this project was relatively simple, an extensive literature review did not reveal any previously published reports describing this type of approach to the distribution of a pharmacy bulletin. The development and implementation of the electronic drug and therapeutics bulletin has provided an opportunity to use modern communication technology to promote safe and effective medication use and appears to have been well received.

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