Microstructural impacts on ionic conductivity of oxide solid electrolytes from a combined atomistic-mesoscale approach

Although multiple oxide-based solid electrolyte materials with intrinsically high ionic conductivities have emerged, practical processing and synthesis routes introduce grain boundaries and other interfaces that can perturb primary conduction channels. To directly probe these effects, we demonstrate an efficient and general mesoscopic computational method capable of predicting effective ionic conductivity through a complex polycrystalline oxide-based solid electrolyte microstructure without relying on simplified equivalent circuit description. We parameterize the framework for Li7-xLa3Zr2O12 (LLZO) garnet solid electrolyte by combining synthetic microstructures from phase-field simulations with diffusivities from molecular dynamics simulations of ordered and disordered systems. Systematically designed simulations reveal an interdependence between atomistic and mesoscopic microstructural impacts on the effective ionic conductivity of polycrystalline LLZO, quantified by newly defined metrics that characterize the complex ionic transport mechanism. Our results provide fundamental understanding of the physical origins of the reported variability in ionic conductivities based on an extensive analysis of literature data, while simultaneously outlining practical design guidance for achieving desired ionic transport properties based on conditions for which sensitivity to microstructural features is highest. Additional implications of our results are discussed, including a possible connection between ion conduction behavior and dendrite formation.

Model Order Reduction for Lumped RC Transmission Lines

<div>We start with a detailed review of the PACT approach for model order reduction of RC networks. We then develop a method that uses PACT as a preprocessing step to transform a generic lumped RC transmission line of some nominal order, based on a nominal (r,c) setting, into a parameterized circuit captured in a SPICE sub-circuit description. Then, given any other lumped RC line of the same order, we pass its (r,c) setting as parameters to this sub-circuit so as to automatically transform and reduce the line into a reduced order model without having to rerun PACT. In this way, we effectively characterize lumped RC transmission lines in a way that allows them to be reduced on-the-fly without any expensive processing.</div>

Model Order Reduction for Lumped RC Transmission Lines

<div>We start with a detailed review of the PACT approach for model order reduction of RC networks. We then develop a method that uses PACT as a preprocessing step to transform a generic lumped RC transmission line of some nominal order, based on a nominal (r,c) setting, into a parameterized circuit captured in a SPICE sub-circuit description. Then, given any other lumped RC line of the same order, we pass its (r,c) setting as parameters to this sub-circuit so as to automatically transform and reduce the line into a reduced order model without having to rerun PACT. In this way, we effectively characterize lumped RC transmission lines in a way that allows them to be reduced on-the-fly without any expensive processing.</div>

Checking Application Level Properties Using Assertion Synthesis

This work presents a proof-of-concept of a new approach on automatic generation of digital hardware that is able to check application-level properties of an embedded system such as a faulty system behavior at runtime. The approach makes use of assertion-based verification setups that today are very common in the area of digital hardware design with, however, the sole focus on logic simulation. Thus, a PSL-to-VHDL compiler is introduced that generates VHDL (Very High Speed Integrated Circuit Description Language) code out of PSL (Property Specification Language) assertions which can be further processed by a traditional digital logic synthesis tool. That way, runtime checker units can be automatically generated with little effort because of the already existing assertion-based test benches. Furthermore, a model railway demonstrator is presented herein as an example for a safety-critical application to prove the proposed tool flow on a use case. Implementation results based on that use case are discussed. Finally, the paper concludes with a brief outlook on related future work of the authors.

Reaction Systems and Synchronous Digital Circuits

A reaction system is a modeling framework for investigating the functioning of the living cell, focused on capturing cause–effect relationships in biochemical environments. Biochemical processes in this framework are seen to interact with each other by producing the ingredients enabling and/or inhibiting other reactions. They can also be influenced by the environment seen as a systematic driver of the processes through the ingredients brought into the cellular environment. In this paper, the first attempt is made to implement reaction systems in the hardware. We first show a tight relation between reaction systems and synchronous digital circuits, generally used for digital electronics design. We describe the algorithms allowing us to translate one model to the other one, while keeping the same behavior and similar size. We also develop a compiler translating a reaction systems description into hardware circuit description using field-programming gate arrays (FPGA) technology, leading to high performance, hardware-based simulations of reaction systems. This work also opens a novel interesting perspective of analyzing the behavior of biological systems using established industrial tools from electronic circuits design.

Notification-Oriented Paradigm to Implement Digital Hardware

The growing demand for high-performance digital circuits, mainly involving FPGAs, increases the demand for high-level synthesis (HLS) tools. Traditional Hardware Description Languages (HDLs) are complex and depend on low-level abstractions, thereby requiring hardware detailed knowledge from developers. In turn, the current HLS tools are based on proprietary or C/C[Formula: see text] derived languages, which allow easier circuit description but decrease performance. This work presents an alternative solution for designing digital circuits, which arises from the Notification-Oriented Paradigm (NOP). The NOP is an alternative computing solution based upon a set of predefined interconnected entities whose collaborations are performed through precise notifications. The NOP, when targeted to digital hardware (DH), allows the developer to describe the circuit behavior just by connecting and parameterizing elements. The result is a VHDL file that can be compiled for any platform from any manufacturer. In order to check the functionality of this approach, sorting circuits were built both with usual VHDL and with the NOP VHDL aiming to compare the resulting circuits in terms of operating frequency and resource use. The results show that the NOP VHDL approach facilitates the build of digital circuits when compared to the VHDL usual approach without limiting the operating frequency or increasing the use of resources.

On Definition of Operator o for Weakly Nonlinear Circuits

For the first time, operator o appeared in the literature on weakly nonlinear circuits in a Narayanan’s paper on modelling transistor nonlinear distortion with the use of Volterra series. Its definition was restricted only to the linear part of a nonlinear circuit description. Obviously, as we show here, Narayanan’s operator o had meaning of a linear convolution integral. The extended version of this operator, which was applied to the whole nonlinear circuit representation by the Volterra series, was introduced by Meyer and Stephens in their paper on modelling nonlinear distortion in variable-capacitance diodes. We show here that its definition as well as another definition communicated to the author of this paper are faulty. We draw here attention to these facts because the faults made by Meyer and Stephens were afterwards replicated in publications of Palumbo and his coworkers on harmonic distortion calculation in integrated CMOS amplifiers, and recently in a paper about distortion analysis of parametric amplifier by H. Shrimali and S. Chatterjee. These faults are also present in some class notes for students, which are available on WWW-pages.