scholarly journals Dynamic Hardware Development

2008 ◽  
Vol 2008 ◽  
pp. 1-10 ◽  
Author(s):  
Stephen Craven ◽  
Peter Athanas
Keyword(s):  
Digital Design ◽  
Development Environment ◽  
Dynamically Reconfigurable ◽  
Reconfigurable Design ◽  
Synthesis Tool ◽  
Embedded Controller ◽  
Hardware Description ◽  
Description Languages ◽  
High Level ◽  
Tools And Techniques

Applications that leverage the dynamic partial reconfigurability of modern FPGAs are few, owing in large part to the lack of suitable tools and techniques to create them. While the trend in digital design is towards higher levels of design abstractions, forgoing hardware description languages in some cases for high-level languages, the development of a reconfigurable design requires developers to work at a low level and contend with many poorly documented architecture-specific aspects. This paper discusses the creation of a high-level development environment for reconfigurable designs that leverage an existing high-level synthesis tool to enable the design, simulation, and implementation of dynamically reconfigurable hardware solely from a specification written in C. Unlike previous attempts, this approach encompasses the entirety of design and implementation, enables self-re-configuration through an embedded controller, and inherently handles partial reconfiguration. Benchmarking numbers are provided, which validate the productivity enhancements this approach provides.

scholarly journals Hybrid Model: An Efficient Symmetric Multiprocessor Reference Model

2015 ◽  
Vol 2015 ◽  
pp. 1-10
Author(s):  
Shupeng Wang ◽  
Kai Huang ◽  
Tianyi Xie ◽  
Xiaolang Yan
Keyword(s):  
Hybrid Model ◽  
Reference Model ◽  
Cost Effective ◽  
Functional Verification ◽  
Simulation Based ◽  
Design Resources ◽  
Hardware Description ◽  
Description Languages ◽  
High Level ◽  
The Cost

Functional verification has become one of the main bottlenecks in the cost-effective design of embedded systems, particularly for symmetric multiprocessors. It is estimated that verification in its entirety accounts for up to 60% of design resources, including duration, computer resources, and total personnel. Simulation-based verification is a long-standing approach used to locate design errors in the symmetric multiprocessor verification. The greatest challenge of simulation-based verification is the creation of the reference model of the symmetric multiprocessor. In this paper, we propose an efficient symmetric multiprocessor reference model, Hybrid Model, written with SystemC. SystemC can provide a high-level simulation environment and is faster than the traditional hardware description languages. Hybrid Model has been implemented in an efficient 32-bit symmetric multiprocessor verification. Experimental results show our proposed model is a fast, accurate, and efficient symmetric multiprocessor reference model and it is able to help designers to locate design errors easily and accurately.

Experiences with High-Level Design and Modelling of Digital Systems

1995 ◽  
Vol 32 (4) ◽  
pp. 333-340
Author(s):  
S. J. Sangwine
Keyword(s):  
Digital Systems ◽  
Hardware Description Languages ◽  
Transversal Filter ◽  
Hardware Description ◽  
Ieee Standard ◽  
Level Design ◽  
Description Languages ◽  
High Level ◽  
The University

Experiences with high-level design and modelling of digital systems Design and modelling of digital systems has been taught at the University of Reading for six years, using Silvar-Lisco HELIX and lately IEEE Standard VHDL hardware description languages. Three exercises have been used throughout this time. These are: modelling of a multiplier-accumulator, design and modelling of a transversal filter, and specification-level modelling of a FIFO.

scholarly journals A considerable improvement of the traditional FPGA-based digital design methodology by using an Arduino sensor board

2019 ◽  
Author(s):  
Marcos Martinez Peiro ◽  
Miguel Larrea Torres ◽  
Jose-Vte Lidón Roger ◽  
Yolanda Jiménez Jiménez ◽  
Rubén Torres-Curado ◽  
...  
Keyword(s):  
Digital Design ◽  
Digital Systems ◽  
Sensor Data ◽  
Data Converter ◽  
Serial Data ◽  
Field Programmable ◽  
Ultrasound Sensor ◽  
Hardware Description ◽  
The Subject ◽  
Description Languages

The traditional way to learn and teach Digital Systems has been changing over the last decades by the use of Hardware Description Languages (HDL) and Field Programmable Gate Array (FPGA) evaluation boards. The use of an Arduino development kit with different sensors connected to the FPGA upsizes the students experience in the area of Digital Systems. A temperature and humidity ambience sensor combined with an ultrasound sensor to measure distance can effectively be used by students to implement its first serial data converter that takes the sensor data and shows the obtained values from the Arduino in the seven segment display of the FPGA kit. After three years of experience in the new grade courses at the UPV Telecommunication School the number of students enjoying this new way to learn the subject Fundamentals of Digital Electronics (FSD) has dramatically risen up with an increase of a 20% in the number of students that pass the subject and that select the electronic branch of telecommunication studies in the future semesters

Notification-Oriented Paradigm to Implement Digital Hardware

2018 ◽  
Vol 27 (08) ◽  
pp. 1850124 ◽  
Author(s):  
Ricardo Kerschbaumer ◽  
Robson R. Linhares ◽  
Jean M. Simão ◽  
Paulo C. Stadzisz ◽  
Carlos R. Erig Lima
Keyword(s):  
High Performance ◽  
Digital Circuits ◽  
Operating Frequency ◽  
Detailed Knowledge ◽  
Use Of Resources ◽  
Digital Hardware ◽  
Hardware Description ◽  
Description Languages ◽  
Circuit Description ◽  
High Level

The growing demand for high-performance digital circuits, mainly involving FPGAs, increases the demand for high-level synthesis (HLS) tools. Traditional Hardware Description Languages (HDLs) are complex and depend on low-level abstractions, thereby requiring hardware detailed knowledge from developers. In turn, the current HLS tools are based on proprietary or C/C[Formula: see text] derived languages, which allow easier circuit description but decrease performance. This work presents an alternative solution for designing digital circuits, which arises from the Notification-Oriented Paradigm (NOP). The NOP is an alternative computing solution based upon a set of predefined interconnected entities whose collaborations are performed through precise notifications. The NOP, when targeted to digital hardware (DH), allows the developer to describe the circuit behavior just by connecting and parameterizing elements. The result is a VHDL file that can be compiled for any platform from any manufacturer. In order to check the functionality of this approach, sorting circuits were built both with usual VHDL and with the NOP VHDL aiming to compare the resulting circuits in terms of operating frequency and resource use. The results show that the NOP VHDL approach facilitates the build of digital circuits when compared to the VHDL usual approach without limiting the operating frequency or increasing the use of resources.

Graphical Hardware Description as a High-Level Design Entry Method for FPGA-Based Data Acquisition Systems

2014 ◽  
Vol 613 ◽  
pp. 296-306
Author(s):  
Christoph Landmann ◽  
Rolf Kall
Keyword(s):  
Data Acquisition ◽  
Heterogeneous Computing ◽  
Digital Signal ◽  
Hardware Description Languages ◽  
Generic Properties ◽  
Development Environment ◽  
Real Time System ◽  
Data Acquisition Systems ◽  
Hardware Description ◽  
Description Languages

Probably one of the most significant developments in the field of software-defined multifunction data acquisition systems and devices is the employment of FPGA (Field-Programmable GateArray) technology, resulting in a tremendous digital processing potential close to the I/O pin. FPGA technology is based on reconfigurable semiconductor devices which can be employed as processing targets in heterogeneous computing architectures for a variety of data acquisition applications. They can primarily be characterized by generic properties, such as deterministic execution, inherent parallelism, fast processing speed and high availability, stability and reliability. Therefore FPGAs areparticularly suitable for use in “intelligent” data acquisition applications that require either in-line digital signal co-processing or real-time system emulation in the field of advanced control, protocol aware communication, hardware-in-the-loop (HIL) as well as RF and wireless test. From the perspective of a domain expert however, primarily being focused on developing applications and algorithms, simple and intuitive design entry methods and tools are required that facilitate the FPGA configuration and design entry process. Traditional FPGA design entry methods and commercially available tools assume a comprehensive knowledge of hardware description languages (HDL),such as VHDL or Verilog®, and implement a process or function at register-level. In contrast, graphical hardware description languages for FPGAs, such as the integrated development environment NI LabVIEW® with FPGA module extension, abstract the design process by means of graphical objects, I/O nodes and interconnecting wires that represent the FPGA’s IP and implement processes, timing, I/O integration and data flow. This paper discusses the advantages of graphical system design for FPGAs over text-based alternatives, introduces interfaces for the integration of 3rd party IP, all backed up by a detailed illustration of a COTS FPGA-based multifunction DAQ target compared to a traditional DAQ architecture.

scholarly journals Why Are Hardware Description Languages Important for Hardware Design Courses?

2021 ◽  
Vol 17 (2) ◽  
pp. 1-16
Author(s):  
Raghad Obeidat ◽  
Hussein Alzoubi
Keyword(s):  
Computer Architecture ◽  
Programming Languages ◽  
Hardware Design ◽  
Logic Design ◽  
Hardware Description Languages ◽  
Computer Engineering ◽  
Hardware Description ◽  
Description Languages ◽  
High Level ◽  
Hardware Designs

Curricula in computer engineering, computer science, and other related fields include several courses about hardware design. Examples of these courses are digital logic design, computer architecture, microprocessors, computer interfacing, hardware design, embedded systems, switching theorem, and others. In order for the students to realize the concepts taught in such courses, practical track should be reinforced along with the theoretical track. Many universities offer to their students labs in which they can practice hardware design. However, students need more than that: they need tools that enable them to design, model, simulate, synthesize, and implement hardware designs. Although high-level programming languages like Java and C++ could be an option, it might be a tedious task to use them for this mission. Fortunately, hardware-description languages (HDLs) have been specifically devised for this purpose. This paper shows some of the great features of HDLs and compare using them with using C++ for illustrating digital concepts through salient examples.

scholarly journals Functional Verification of Large-integers Circuits using a Cosimulation-based Approach

2017 ◽  
Vol 7 (4) ◽  
pp. 2192
Author(s):  
Nejmeddine Alimi ◽  
Younes Lahbib ◽  
Mohsen Machhout ◽  
Rached Tourki
Keyword(s):  
Good Evidence ◽  
Modular Arithmetic ◽  
Functional Verification ◽  
Hardware Description Languages ◽  
Abstraction Level ◽  
Hardware Description ◽  
Multi Level ◽  
Description Languages ◽  
High Level ◽  
Real Challenge

Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer’s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability.

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