scholarly journals A New CDS Structure for High Density FPA with Low Power

VLSI Design ◽  
2015 ◽  
Vol 2015 ◽  
pp. 1-7 ◽  
Author(s):  
Xiao Wang ◽  
Zelin Shi
Keyword(s):  
Integrated Circuit ◽  
Dominant Role ◽  
Noise Analysis ◽  
Calculation Model ◽  
High Density ◽  
Integration Time ◽  
Subthreshold Region ◽  
Readout Integrated Circuit ◽  
Long Wave ◽  
Layout Area

Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS) circuits play important roles in both depressing reset noise and conditioning integration signals. To adapt applications for focal planes of large format and high density, a new structure of CDS circuit occupying small layout area is proposed, whose power dissipation has been optimized by using MOSFETs in operation of subthreshold region, which leads to 720 nW. Then the noise calculation model is established, based on which the noise analysis has been carried out by the approaches of transfer function and numerical simulations using SIMULINK and Verilog-A. The results are in good agreement, demonstrating the validity of the present noise calculation model. Thermal noise plays a dominant role in the long wave situation while 1/f noise is the majority in the medium wave situation. The total noise of long wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing.

scholarly journals A Modularized Noise Analysis Method with Its Application in Readout Circuit Design

VLSI Design ◽  
2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Xiao Wang ◽  
Zelin Shi ◽  
Baoshu Xu
Keyword(s):  
Integrated Circuit ◽  
Transfer Functions ◽  
Noise Source ◽  
Noise Analysis ◽  
Noise Model ◽  
Analysis Method ◽  
Noise Performance ◽  
Subthreshold Region ◽  
Readout Integrated Circuit ◽  
Output Noise

A readout integrated circuit (ROIC) is a crucial part that determines the quality of imaging. In order to analyze the noise of a ROIC with distinct illustration of each noise source transferring, a modularized noise analysis method is proposed whose application is applied for a ROIC cell, where all the MOSFETs are optimized in subthreshold region, leading to the power dissipation 2.8 μW. The modularized noise analysis begins with the noise model built using transfer functions and afterwards presents the transfer process of noise in the form of matrix, through which we can describe the contribution of each noise source to the whole output noise clearly, besides optimizing the values of key components. The optimal noise performance is obtained under the limitation of layout area less than 30 μm × 30 μm, resulting in that the integration capacitor should be selected as 0.74 pF to achieve an optimal noise performance, the whole output noise reaching the minimum value at 74.1 μV. In the end transient simulations utilizing Verilog-A are carried out for comparisons. The results showing good agreement verify the feasibility of the method presented through matrix.

Weak-Light Readout Collection on the Quantum Effect Photoelectric Sensor

2012 ◽  
Vol 465 ◽  
pp. 296-299
Author(s):  
S.H. Zhang ◽  
M.J. Wang ◽  
Fang Min Guo
Keyword(s):  
Integrated Circuit ◽  
Quantum Effect ◽  
High Sensitivity ◽  
Integration Time ◽  
Voltage Response ◽  
Readout Integrated Circuit ◽  
Response Voltage ◽  
Photoelectric Sensor ◽  
Circuit Integration ◽  
Weak Light

The weak-light characteristics of the GaAs/InGaAs quantum effect photoelectric sensor are presented. In order to explore its higher sensitive application because of higher quantum efficiency, a readout integrated circuit (ROIC) of the capacitor feedback transimpendance amplifier (CTIA) was designed to deal with voltage response of novel sensor. The readout circuit integration was designed to match 2×8 the photoelectric sensor array. A 633nm laser beam shot to the window of sensor with radiation intensity 2nW the readout response voltage was 225mV and 4.5E +07V /W responsivity at 120K and 44.8μs integration time when biased voltage up to -3V. Even under 0.5nw shooting,we still can see the high sensitivity.

Dependence of the Deformation of 128×128 InSb Focal-plane Arrays on the Silicon Readout Integrated Circuit Thickness

2015 ◽  
Vol 9 (1) ◽  
pp. 170-174 ◽  
Author(s):  
Xiaoling Zhang ◽  
Qingduan Meng ◽  
Liwen Zhang
Keyword(s):  
Thermal Shock ◽  
Indium Antimonide ◽  
Integrated Circuit ◽  
Focal Plane ◽  
Three Dimensional ◽  
Fracture Probability ◽  
Focal Plane Arrays ◽  
Thermal Shock Test ◽  
Readout Integrated Circuit ◽  
Three Dimensional Modeling

The square checkerboard buckling deformation appearing in indium antimonide infrared focal-plane arrays (InSb IRFPAs) subjected to the thermal shock tests, results in the fracturing of the InSb chip, which restricts its final yield. In light of the proposed three-dimensional modeling, we proposed the method of thinning a silicon readout integrated circuit (ROIC) to level the uneven top surface of InSb IRFPAs. Simulation results show that when the silicon ROIC is thinned from 300 μm to 20 μm, the maximal displacement in the InSb IRFPAs linearly decreases from 7.115 μm to 0.670 μm in the upward direction, and also decreases linearly from 14.013 μm to 1.612 μm in the downward direction. Once the thickness of the silicon ROIC is less than 50 μm, the square checkerboard buckling deformation distribution presenting in the thicker InSb IRFPAs disappears, and the top surface of the InSb IRFPAs becomes flat. All these findings imply that the thickness of the silicon ROIC determines the degree of deformation in the InSb IRFPAs under a thermal shock test, that the method of thinning a silicon ROIC is suitable for decreasing the fracture probability of the InSb chip, and that this approach improves the reliability of InSb IRFPAs.

Advanced readout integrated circuit signal processing

2006 ◽  
Author(s):  
Allen Hairston ◽  
James Stobie ◽  
Rosanne Tinkler
Keyword(s):  
Signal Processing ◽  
Integrated Circuit ◽  
Readout Integrated Circuit
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