scholarly journals A Modularized Noise Analysis Method with Its Application in Readout Circuit Design

VLSI Design ◽  
2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Xiao Wang ◽  
Zelin Shi ◽  
Baoshu Xu
Keyword(s):  
Integrated Circuit ◽  
Transfer Functions ◽  
Noise Source ◽  
Noise Analysis ◽  
Noise Model ◽  
Analysis Method ◽  
Noise Performance ◽  
Subthreshold Region ◽  
Readout Integrated Circuit ◽  
Output Noise

A readout integrated circuit (ROIC) is a crucial part that determines the quality of imaging. In order to analyze the noise of a ROIC with distinct illustration of each noise source transferring, a modularized noise analysis method is proposed whose application is applied for a ROIC cell, where all the MOSFETs are optimized in subthreshold region, leading to the power dissipation 2.8 μW. The modularized noise analysis begins with the noise model built using transfer functions and afterwards presents the transfer process of noise in the form of matrix, through which we can describe the contribution of each noise source to the whole output noise clearly, besides optimizing the values of key components. The optimal noise performance is obtained under the limitation of layout area less than 30 μm × 30 μm, resulting in that the integration capacitor should be selected as 0.74 pF to achieve an optimal noise performance, the whole output noise reaching the minimum value at 74.1 μV. In the end transient simulations utilizing Verilog-A are carried out for comparisons. The results showing good agreement verify the feasibility of the method presented through matrix.

scholarly journals A New CDS Structure for High Density FPA with Low Power

VLSI Design ◽  
2015 ◽  
Vol 2015 ◽  
pp. 1-7 ◽  
Author(s):  
Xiao Wang ◽  
Zelin Shi
Keyword(s):  
Integrated Circuit ◽  
Dominant Role ◽  
Noise Analysis ◽  
Calculation Model ◽  
High Density ◽  
Integration Time ◽  
Subthreshold Region ◽  
Readout Integrated Circuit ◽  
Long Wave ◽  
Layout Area

Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS) circuits play important roles in both depressing reset noise and conditioning integration signals. To adapt applications for focal planes of large format and high density, a new structure of CDS circuit occupying small layout area is proposed, whose power dissipation has been optimized by using MOSFETs in operation of subthreshold region, which leads to 720 nW. Then the noise calculation model is established, based on which the noise analysis has been carried out by the approaches of transfer function and numerical simulations using SIMULINK and Verilog-A. The results are in good agreement, demonstrating the validity of the present noise calculation model. Thermal noise plays a dominant role in the long wave situation while 1/f noise is the majority in the medium wave situation. The total noise of long wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing.

scholarly journals Prediction of Noise Performance of Ro-Ro Passenger Ship by the Hybrid Statistical Energy Analysi

2018 ◽  
Vol 2 (Special edition 2) ◽  
pp. 29-45
Author(s):  
Nikola Vladimir ◽  
Ivan Lončar ◽  
Ivica Aničić ◽  
Ivo Senjanović
Keyword(s):  
Noise Source ◽  
Noise Analysis ◽  
Noise Model ◽  
Design Parameters ◽  
Sound Insulation ◽  
Noise Prediction ◽  
Noise Performance ◽  
Noise Levels ◽  
Technical Data ◽  
Passenger Ship

Noise prediction on board Ro-Ro passenger ship with a capacity of 145 cars and 600 passengers has been performed by means of the hybrid Statistical Energy Analysis (SEA). A general commercial noise analysis software Designer-NOISE is used. Basic issues related to noise on board ships are described, with particular emphasis to regulatory framework. An outline of the used software is presented together with ship technical data and noise source overview. Noise model is described in details and results are presented for selected compartments both without and with sound insulation. In addition to standard noise prediction output, a sensitivity analysis of noise levels with respect to some design parameters (wall thickness, insulation type and thickness, etc.) has been performed. Finally, conclusions on noise performance of a ship are drawn.

Dependence of the Deformation of 128×128 InSb Focal-plane Arrays on the Silicon Readout Integrated Circuit Thickness

2015 ◽  
Vol 9 (1) ◽  
pp. 170-174 ◽  
Author(s):  
Xiaoling Zhang ◽  
Qingduan Meng ◽  
Liwen Zhang
Keyword(s):  
Thermal Shock ◽  
Indium Antimonide ◽  
Integrated Circuit ◽  
Focal Plane ◽  
Three Dimensional ◽  
Fracture Probability ◽  
Focal Plane Arrays ◽  
Thermal Shock Test ◽  
Readout Integrated Circuit ◽  
Three Dimensional Modeling

The square checkerboard buckling deformation appearing in indium antimonide infrared focal-plane arrays (InSb IRFPAs) subjected to the thermal shock tests, results in the fracturing of the InSb chip, which restricts its final yield. In light of the proposed three-dimensional modeling, we proposed the method of thinning a silicon readout integrated circuit (ROIC) to level the uneven top surface of InSb IRFPAs. Simulation results show that when the silicon ROIC is thinned from 300 μm to 20 μm, the maximal displacement in the InSb IRFPAs linearly decreases from 7.115 μm to 0.670 μm in the upward direction, and also decreases linearly from 14.013 μm to 1.612 μm in the downward direction. Once the thickness of the silicon ROIC is less than 50 μm, the square checkerboard buckling deformation distribution presenting in the thicker InSb IRFPAs disappears, and the top surface of the InSb IRFPAs becomes flat. All these findings imply that the thickness of the silicon ROIC determines the degree of deformation in the InSb IRFPAs under a thermal shock test, that the method of thinning a silicon ROIC is suitable for decreasing the fracture probability of the InSb chip, and that this approach improves the reliability of InSb IRFPAs.

Ring Oscillator Phase Noise Properties due to PSN with Deterministic Frequency

2012 ◽  
Vol 496 ◽  
pp. 527-533
Author(s):  
Na Bai ◽  
Hong Gang Zhou ◽  
Qiu Lei Wu ◽  
Chun Yu Peng
Keyword(s):  
Phase Noise ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Analysis Method ◽  
Noise Performance ◽  
Supply Noise ◽  
Total Phase ◽  
Phase Noise Performance ◽  
Oscillator Phase Noise ◽  
Oscillator Phase

In this paper, ring oscillator phase noise caused by power supply noise (PSN) with deterministic frequency is analyzed. Results show that phase noise caused by deterministic noise is only an impulse series. Compared with the jitter caused by PSN, the phase noise caused by PSN with deterministic frequency contributes considerably less to total phase noise performance. To verify the analysis method, a CMOS ring oscillator is designed and fabricated using SMIC 0.13 µm CMOS process. Comparisons between the analytical results and measurements prove the accuracy of the proposed method

Advanced readout integrated circuit signal processing

2006 ◽  
Author(s):  
Allen Hairston ◽  
James Stobie ◽  
Rosanne Tinkler
Keyword(s):  
Signal Processing ◽  
Integrated Circuit ◽  
Readout Integrated Circuit
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