scholarly journals Charge-Trapping Devices Using Multilayered Dielectrics for Nonvolatile Memory Applications

2013 ◽  
Vol 2013 ◽  
pp. 1-5
Author(s):  
Wen-Chieh Shih ◽  
Chih-Hao Cheng ◽  
Joseph Ya-min Lee ◽  
Fu-Chien Chiu
Keyword(s):  
Nonvolatile Memory ◽  
Field Effect Transistors ◽  
Charge Trapping ◽  
Memory Window ◽  
Electrical Characteristics ◽  
Data Retention ◽  
Device Structure ◽  
Threshold Voltage Shift ◽  
Memory Applications ◽  
Trapping Devices

Charge-trapping devices using multilayered dielectrics were studied for nonvolatile memory applications. The device structure is Al/Y2O3/Ta2O5/SiO2/Si (MYTOS). The MYTOS field effect transistors were fabricated using Ta2O5as the charge storage layer and Y2O3as the blocking layer. The electrical characteristics of memory window, program/erase characteristics, and data retention were examined. The memory window is about 1.6 V. Using a pulse voltage of 6 V, a threshold voltage shift of ~1 V can be achieved within 10 ns. The MYTOS transistors can retain a memory window of 0.81 V for 10 years.

scholarly journals High Pressure Deuterium Passivation of Charge Trapping Layer for Nonvolatile Memory Applications

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1316
Author(s):  
Jae-Young Sung ◽  
Jun-Kyo Jeong ◽  
Woon-San Ko ◽  
Jun-Ho Byun ◽  
Hi-Deok Lee ◽  
...  
Keyword(s):  
High Pressure ◽  
Nonvolatile Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Trap Density ◽  
Flat Band ◽  
Data Retention ◽  
Retention Model ◽  
A Charge ◽  
Memory Applications

In this study, the deuterium passivation effect of silicon nitride (Si3N4) on data retention characteristics is investigated in a Metal-Nitride-Oxide-Silicon (MNOS) memory device. To focus on trap passivation in Si3N4 as a charge trapping layer, deuterium (D2) high pressure annealing (HPA) was applied after Si3N4 deposition. Flat band voltage shifts (ΔVFB) in data retention mode were compared by CV measurement after D2 HPA, which shows that the memory window decreases but charge loss in retention mode after program is suppressed. Trap energy distribution based on thermal activated retention model is extracted to compare the trap density of Si3N4. D2 HPA reduces the amount of trap densities in the band gap range of 1.06–1.18 eV. SIMS profiles are used to analyze the D2 profile in Si3N4. The results show that deuterium diffuses into the Si3N4 and exists up to the Si3N4-SiO2 interface region during post-annealing process, which seems to lower the trap density and improve the memory reliability.

scholarly journals LaTiON/LaON as band-engineered charge-trapping layer for nonvolatile memory applications

2012 ◽  
Vol 108 (1) ◽  
pp. 229-234 ◽  
Author(s):  
X. D. Huang ◽  
P. T. Lai ◽  
Johnny K. O. Sin
Keyword(s):  
Nonvolatile Memory ◽  
Charge Trapping ◽  
Memory Applications

Charge Storage Characteristics of Si-Rich Silicon Nitride and the Effect of Tunneling Thickness on Nonvolatile Memory Performance

2011 ◽  
Vol 181-182 ◽  
pp. 307-311
Author(s):  
Hong Hanh Nguyen ◽  
Ngoc Son Dang ◽  
Van Duy Nguyen ◽  
Kyungsoo Jang ◽  
Kyunghyun Baek ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Nonvolatile Memory ◽  
Memory Performance ◽  
Charge Trapping ◽  
Oxide Thickness ◽  
Memory Window ◽  
Charge Storage ◽  
Operating Voltage ◽  
Silicon Clusters ◽  
Retention Characteristics

Nonvolatile memory (NVM) devices with nitride-nitride-oxynitride (NNO) stack structure using Si-rich silicon nitride (SiNx) as charge trapping layer on glass substrate were fabricated. Amorphous silicon clusters existing in the Si-rich SiNxlayer enhance the charge storage capacity of the devices. Low temperature poly-silicon (LTPS) technology, plasma-assisted oxidation/nitridation method to form a uniform ultra-thin tunneling layer, and an optimal Si-rich SiNxcharge trapping layer were used to fabricate NNO NVM devices with different tunneling thickness 2.3, 2.6 and 2.9 nm. The increase memory window, lower voltage operation but little scarifying in retention characteristics of nitride trap NVM devices had been accomplished by reducing the tunnel oxide thickness. The fabricated NVM devices with 2.9 nm tunneling thickness shows excellent electrical properties, such as a low threshold voltage, a high ON/OFF current ratio, a low operating voltage of less than ±9 V and a large memory window of 2.7 V, which remained greater than 72% over a period of 10 years.

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