scholarly journals Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks

2012 ◽  
Vol 2012 ◽  
pp. 1-19 ◽  
Author(s):  
Po-Tsang Huang ◽  
Wei Hwang
Keyword(s):  
Energy Consumption ◽  
Energy Efficient ◽  
Interconnection Networks ◽  
Cmos Technology ◽  
Voltage Scaling ◽  
Scaling Technique ◽  
Coding Scheme ◽  
On Chip ◽  
Reliable Mechanism ◽  
Voltage Swing

Energy-efficient and reliable channels are provided for on-chip interconnection networks (OCINs) using a self-calibrated voltage scaling technique with self-corrected green (SCG) coding scheme. This self-calibrated low-power coding and voltage scaling technique increases reliability and reduces energy consumption simultaneously. The SCG coding is a joint bus and error correction coding scheme that provides a reliable mechanism for channels. In addition, it achieves a significant reduction in energy consumption via a joint triplication bus power model for crosstalk avoidance. Based on SCG coding scheme, the proposed self-calibrated voltage scaling technique adjusts voltage swing for energy reduction. Furthermore, this technique tolerates timing variations. Based on UMC 65 nm CMOS technology, the proposed channels reduces energy consumption by nearly 28.3% compared with that for uncoded channels at the lowest voltage. This approach makes the channels of OCINs tolerant of transient malfunctions and realizes energy efficiency.

scholarly journals A Practical Evaluation on RSA and ECC-Based Cipher Suites for IoT High-Security Energy-Efficient Fog and Mist Computing Devices

Sensors ◽  
2018 ◽  
Vol 18 (11) ◽  
pp. 3868 ◽  
Author(s):  
Manuel Suárez-Albela ◽  
Paula Fraga-Lamas ◽  
Tiago Fernández-Caramés
Keyword(s):  
Energy Consumption ◽  
Energy Efficient ◽  
Fog Computing ◽  
Transport Layer ◽  
Security Level ◽  
Sensors And Actuators ◽  
Computing Paradigm ◽  
Data Throughput ◽  
High Security ◽  
On Chip

The latest Internet of Things (IoT) edge-centric architectures allow for unburdening higher layers from part of their computational and data processing requirements. In the specific case of fog computing systems, they reduce greatly the requirements of cloud-centric systems by processing in fog gateways part of the data generated by end devices, thus providing services that were previously offered by a remote cloud. Thanks to recent advances in System-on-Chip (SoC) energy efficiency, it is currently possible to create IoT end devices with enough computational power to process the data generated by their sensors and actuators while providing complex services, which in recent years derived into the development of the mist computing paradigm. To allow mist computing nodes to provide the previously mentioned benefits and guarantee the same level of security as in other architectures, end-to-end standard security mechanisms need to be implemented. In this paper, a high-security energy-efficient fog and mist computing architecture and a testbed are presented and evaluated. The testbed makes use of Transport Layer Security (TLS) 1.2 Elliptic Curve Cryptography (ECC) and Rivest-Shamir-Adleman (RSA) cipher suites (that comply with the yet to come TLS 1.3 standard requirements), which are evaluated and compared in terms of energy consumption and data throughput for a fog gateway and two mist end devices. The obtained results allow a conclusion that ECC outperforms RSA in both energy consumption and data throughput for all the tested security levels. Moreover, the importance of selecting a proper ECC curve is demonstrated, showing that, for the tested devices, some curves present worse energy consumption and data throughput than other curves that provide a higher security level. As a result, this article not only presents a novel mist computing testbed, but also provides guidelines for future researchers to find out efficient and secure implementations for advanced IoT devices.

Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique

2011 ◽  
Vol E94-C (1) ◽  
pp. 80-88 ◽  
Author(s):  
Yuji OSAKI ◽  
Tetsuya HIROSE ◽  
Kei MATSUMOTO ◽  
Nobutaka KUROKI ◽  
Masahiro NUMA
Keyword(s):  
Circuit Design ◽  
Supply Voltage ◽  
Digital Circuit ◽  
Voltage Scaling ◽  
Scaling Technique ◽  
Digital Circuit Design ◽  
Subthreshold Cmos ◽  
Supply Voltage Scaling ◽  
On Chip

A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology

2012 ◽  
Vol 47 (1) ◽  
pp. 131-140 ◽  
Author(s):  
Hyun-Woo Lee ◽  
Ki-Han Kim ◽  
Young-Kyoung Choi ◽  
Ju-Hwan Sohn ◽  
Nak-Kyu Park ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Voltage Scaling ◽  
Dynamic Voltage Scaling ◽  
Scaling Technique ◽  
Dynamic Voltage

DELAY AND ENERGY EFFICIENT CODING TECHNIQUES FOR CAPACITIVE INTERCONNECTS

2007 ◽  
Vol 16 (06) ◽  
pp. 929-942
Author(s):  
J. V. R. RAVINDRA ◽  
M. B. SRINIVAS
Keyword(s):  
Energy Consumption ◽  
Cross Talk ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Propagation Delay ◽  
Deep Submicron ◽  
Efficient Coding ◽  
Data Bus ◽  
On Chip ◽  
Important Design

In the current era of deep-submicron technology (DSM), minimizing the propagation delay and energy consumption on buses is the most important design objective in system-on-chip (SOC) designs. In particular, coupling effects between wires on the bus can cause serious problems such as cross-talk delay, noise, and power dissipation. Most of the work reported in literature so far concentrates on either minimizing the energy consumption or the delay. In this paper, the authors propose two coding techniques for achieving energy and delay efficiency in data transmission on on-chip buses. It is shown, using SPEC 2000 benchmark suit, that the proposed techniques achieve an energy saving of 35% or over the un-encoded data on the data bus and eliminate cross-talk-delay classes 6, 5, and 4.

scholarly journals DESIGN OF ENERGY EFFICIENT HYBRID 1-BIT FULL ADDER FOR ARITHMETIC APPLICATIONS

2020 ◽  
Vol 4 (6) ◽  
pp. 15-18
Author(s):  
Haroon Rasheed S ◽  
Mohan Das S ◽  
Samba Sivudu Gaddam
Keyword(s):  
Energy Consumption ◽  
Energy Efficient ◽  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Full Adder ◽  
Cmos Technology ◽  
Internal Logic ◽  
Logic Cells ◽  
Power Delay Product

This paper presents an energy efficient 1-bit full adder designed with a low voltage and high performance internal logic cells which leads to have abridged Power Delay Product (PDP). The customized XNOR and XOR gates, a necessary entity, are also presented. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technology at a supply voltage of 0.9 Volts. The proposed 1-bit adder cell is compared with various trendy adders based on speed, power consumption and energy (PDP). The proposed adder schemes with modified internal entity cells achieve significant savings in terms of delay and energy consumption and which are more than 77% and 40.47% respectively when compared with conventional “C-CMOS” 1-bit full adder and other counter parts.

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