scholarly journals A Very Robust AlGaN/GaN HEMT Technology to High Forward Gate Bias and Current

2012 ◽  
Vol 2012 ◽  
pp. 1-4 ◽  
Author(s):  
Bradley D. Christiansen ◽  
Eric R. Heller ◽  
Ronald A. Coutu ◽  
Ramakrishna Vetury ◽  
Jeffrey B. Shealy
Keyword(s):  
Breakdown Voltage ◽  
Threshold Voltage ◽  
Drain Current ◽  
Conventional Wisdom ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Bias Stress ◽  
Gan Hemt ◽  
Positive Threshold ◽  
Gan Hemts

Reports to date of GaN HEMTs subjected to forward gate bias stress include varied extents of degradation. We report an extremely robust GaN HEMT technology that survived—contrary to conventional wisdom—high forward gate bias (+6 V) and current (>1.8 A/mm) for >17.5 hours exhibiting only a slight change in gate diode characteristic, little decrease in maximum drain current, with only a 0.1 V positive threshold voltage shift, and, remarkably, a persisting breakdown voltage exceeding 200 V.

Research on Threshold Voltage Instability in SiC MOSFET Devices with Precision Measurement

2019 ◽  
Vol 954 ◽  
pp. 133-138
Author(s):  
Ao Liu ◽  
Song Bai ◽  
Run Hua Huang ◽  
Tong Tong Yang ◽  
Hao Liu
Keyword(s):  
Threshold Voltage ◽  
Precision Measurement ◽  
Gate Dielectric ◽  
Interface Traps ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Experimental Platform ◽  
Bias Stress ◽  
Voltage Instability ◽  
Voltage Drift

The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.

Performance of ZnO TFTs with AlN as Insulator

2007 ◽  
Vol 1035 ◽  
Author(s):  
Maria Merlyne De Souza ◽  
Richard B Cross ◽  
Suhas Jejurikar ◽  
K P Adhi
Keyword(s):  
Surface Roughness ◽  
Threshold Voltage ◽  
Rf Sputtering ◽  
Interface States ◽  
Aluminium Nitride ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Positive Threshold ◽  
The Stability

AbstractThe performance of ZnO TFTs fabricated via RF sputtering, with Aluminium Nitride (AlN) as the underlying insulator are reported. The surface roughness of ZnO with AlN is lower than that with SiN by at least 5 times, and that with SiO2 by 30 times. The resulting mobility for the three insulators AlN, SiN, SiO2 using identical process is found to be 3, 0.2-0.7 and 0.1-0.25 cm2/Vs respectively. There does not appear to be any corresponding improvement in the stability of the AlN devices. The devices demonstrate significant positive threshold voltage shift with positive gate bias and negative threshold voltage shift with negative gate bias. The underlying cause is surmised to be ultra-fast interface states in combination with bulk traps in the ZnO.

Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET

2020 ◽  
Vol 1004 ◽  
pp. 554-558
Author(s):  
Kwangwon Lee ◽  
Young Ho Seo ◽  
Taeseop Lee ◽  
Kyeong Seok Park ◽  
Martin Domeij ◽  
...  
Keyword(s):  
High Temperature ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Gate Bias ◽  
Annealed Condition ◽  
Threshold Voltage Shift ◽  
Bias Stress ◽  
Phosphorus Doped ◽  
Gate Bias Stress ◽  
Gate Oxide Integrity

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

Positive Threshold Voltage Shift in AlGaN/GaN HEMTs and E-Mode Operation By ${\mathrm{Al}}_{x}{\mathrm{Ti}}_{1-x}$ O Based Gate Stack Engineering

2019 ◽  
Vol 66 (6) ◽  
pp. 2544-2550 ◽  
Author(s):  
Sayak Dutta Gupta ◽  
Ankit Soni ◽  
Vipin Joshi ◽  
Jeevesh Kumar ◽  
Rudrarup Sengupta ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Stack ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Mode Operation ◽  
Positive Threshold ◽  
Gan Hemts
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