scholarly journals Carrier-Based Common Mode Voltage Control Techniques in Three-Level Diode-Clamped Inverter

2012 ◽  
Vol 2012 ◽  
pp. 1-12 ◽  
Author(s):  
Pradyumn Chaturvedi ◽  
Shailendra Jain ◽  
Pramod Agarwal

Switching converters are used in electric drive applications to produce variable voltage, variable frequency supply which generates harmful large dv/dt and high-frequency common mode voltages (CMV). Multilevel inverters generate lower CMV as compared to conventional two-level inverters. This paper presents simple carrier-based technique to control the common mode voltages in multilevel inverters using different structures of sine-triangle comparison method such as phase disposition (PD), phase opposition disposition (POD) by adding common mode voltage offset signal to actual reference voltage signal. This paper also presented the method to optimize the magnitude of this offset signal to reduce CMV and total harmonic distortion in inverter output voltage. The presented techniques give comparable performance as obtained in complex space vector-based control strategy, in terms of number of commutations, magnitude, and rate of change of CMV and harmonic profile of inverter output voltage. Simulation and experimental results presented confirm the effectiveness of the proposed techniques to control the common mode voltages.

Energies ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 466
Author(s):  
Pawel Szczepankowski ◽  
Natalia Strzelecka ◽  
Enrique Romero-Cadaval

This article presents three variants of the Pulse Width Modulation (PWM) for the Double Square Multiphase type Conventional Matrix Converters (DSM-CMC) supplying loads with the open-end winding. The first variant of PWM offers the ability to obtain zero value of the common-mode voltage at the load’s terminals and applies only six switches within the modulation period. The second proposal archives for less Total Harmonic Distortion (THD) of the generated load voltage. The third variant of modulation concerns maximizing the voltage transfer ratio, minimizing the number of switching, and the common-mode voltage cancellation. The discussed modulations are based on the concept of sinusoidal voltage quadrature signals, which can be an effective alternative to the classic space-vector approach. In the proposed approach, the geometrical arrangement of basic vectors needed to synthesize output voltages is built from the less number of vectors, which is equal to the number of the matrix converter’s terminals. The PWM duty cycle computation is performed using only a second-order determinant of the voltages coordinate matrix without using trigonometric functions. A new approach to the PWM duty cycles computing and the load voltage synthesis by 5 × 5 and 12 × 12 topologies has been verified using the PSIM simulation software.


2019 ◽  
Vol 8 (2) ◽  
pp. 405-413 ◽  
Author(s):  
Ezzidin Hassan Aboadla ◽  
Sheroz Khan ◽  
Mohamed H. Habaebi ◽  
Teddy Surya Gunawan ◽  
Belal A. Hamida ◽  
...  

The main goal of utilizing Selective Harmonic Elimination (SHE) techniques in Multilevel Inverters (MLI) is to produce a high-quality output voltage signal with a minimum Total Harmonic Distortion (THD). By calculating N switching angles, SHE technique can eliminate (N-1) low order odd harmonics of the output voltage waveform. To optimized and obtained these switching angles, N of nonlinear equations should be solved using a numerical method. Modulation index (m) and duty cycle play a big role in selective harmonic elimination technique to obtain a minimum harmonic distortion and desired fundamental component voltage. In this paper, a novel Optimization Harmonic Elimination Technique (OHET) based on SHE scheme is proposed to re-mitigate Total Harmonic Distortion. The performance of seven-level H-bridge cascade inverter is evaluated using PSIM and validated experimentally by developing a purposely built microcontroller-based printed circuit board.


2016 ◽  
Vol 2016 ◽  
pp. 1-8 ◽  
Author(s):  
Xiaoqiang Guo ◽  
Ran He ◽  
Mehdi Narimani

Solar photovoltaic (PV) power plant is an effective way to utilize the renewable energy sources. EMI is one of the major concerns in PV power plant. Typically, the multilevel inverters are used in high voltage PV power plant. However, the conventional multilevel inverters require more semiconductors, which complicate the circuit structure and control algorithm. In this paper, a novel five-level inverter is introduced for the high voltage PV power plant applications. The model of the inverter is analyzed. With the redundant switching states, a new modulation strategy is proposed to reduce the common-mode voltage and EMI. The proposed approach is able to eliminate the common-mode voltage; meanwhile it has the capability of balancing the capacitor voltages. The cosimulation tests with the Matlab/Simulink and S-function are carried out. The results verify the effectiveness of the proposed method.


Author(s):  
Lavanya Nannapaneni ◽  
Venu Gopala Rao

<span style="font-family: &quot;TimesNewRoman,Bold&quot;,&quot;Arial&quot;; font-size: 9pt;">A novel space vector modulation (SVM) method for an indirect matrix converter (IMC) is used to reduce the common -mode voltage (CMV) in the output. The process of selecting required active vectors and to describe the switching sequence in the inverter stage of the IMC is explained in this paper. This novel SVM method used to decrease the peak -to-peak amplitude voltage of CMV without using any external hardware. The other advantage of this SVM method is to reduce the total harmonic distortion of line-to-line output voltage. This new modulation technique is easily implemented through simulation and its results are used to demonstrate the improved performance of the input/output waveforms.</span>


2020 ◽  
Vol 10 (7) ◽  
pp. 2384 ◽  
Author(s):  
Adyr A. Estévez-Bén ◽  
Alfredo Alvarez-Diazcomas ◽  
Gonzalo Macias-Bobadilla ◽  
Juvenal Rodríguez-Reséndiz

The rise in renewable energy has increased the use of DC/AC converters, which transform the direct current to alternating current. These devices, generally called inverters, are mainly used as an interface between clean energy and the grid. It is estimated that 21% of the global electricity generation capacity from renewable sources is supplied by photovoltaic systems. In these systems, a transformer to ensure grid isolation is used. Nevertheless, the transformer makes the system expensive, heavy, bulky and reduces its efficiency. Therefore, transformerless schemes are used to eliminate the mentioned disadvantages. One of the main drawbacks of transformerless topologies is the presence of a leakage current between the physical earth of the grid and the parasitic capacitances of the photovoltaic module terminals. The leakage current depends on the value of the parasitic capacitances of the panel and the common-mode voltage. At the same time, the common-mode voltage depends on the modulation strategy used. Therefore, by the manipulation of the modulation technique, is accomplished a decrease in the leakage current. However, the connection standards for photovoltaic inverters establish a maximum total harmonic distortion of 5%. In this paper an analysis of the common-mode voltage and its influence on the value of the leakage current is described. The main topologies and strategies used to reduce the leakage current in transformerless schemes are summarized, highlighting advantages and disadvantages and establishing points of comparison with similar topologies. A comparative table with the most important aspects of each converter is shown based on number of components, modes of operation, type of modulation strategy used, and the leakage current value obtained. It is important to mention that analyzed topologies present a variation of the leakage current between 0 to 180 mA. Finally, the trends, problems, and researches on transformerless grid-connected PV systems are discussed.


Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 20
Author(s):  
Hao Ding ◽  
Danyu Wu ◽  
Xuqiang Zheng ◽  
Lei Zhou ◽  
Teng Chen ◽  
...  

This paper presents a 20 GS/s four-channel time-interleaved sample-and-hold amplifier (SHA), which aims to improve the harmonic distortion performance, eliminate the common-mode voltage fall in track-to-hold transition, and solve the difficulty of timing mismatch calibration among different sampling channels. In data path, the harmonic distortion of the track-hold switch is optimized by introducing a distortion-improving resistor into the switched emitter follower. The common-mode voltage fall is eliminated by an inserted delay-regulating resistor. Additionally, broadband data buffers are utilized to further guarantee a wide bandwidth. In clock path, an interpolator-based phase regulator in analog domain is implemented to calibrate the timing mismatch, hence avoiding the large area cost and complicated algorithm in the digital domain. Fabricated in a 0.18 μm SiGe BiCMOS process, the experimental results show that the SHA achieves a bandwidth of 16 GHz and a total harmonic distortion of −39.6 to approximately −51.8 dB with a −3 dBm input. By applying the proposed sampling phase regulator, the timing mismatch can be optimized to satisfy the requirement of 6-bit resolution at a 4 × 5 GS/s sampling rate. The proposed SHA shows prominent performance on both bandwidth and linearity, which makes it suitable for ultra-high-speed communication networks.


Author(s):  
Vinh-Quan Nguyen ◽  
QuangTho Tran

Demand of cascaded multilevel inverters in industries of electric drives and renewable energy is increasing due to their large-scale capacity and high voltage. The modulation technique of inverters significantly affects the power quality of the inverter output voltage. This paper proposes a new method of carrier wave modulation using the phase shift keying technique for cascaded multilevel inverters. The phase of a constant frequency carrier wave is changed at an accurate time by an input sinusoidal control signal. This modulation technique is simply implemented and only needs a small memory. It also helps reduce the common mode voltage of inverters in order to suppress the output voltage harmonics. Moreover, the ability to reduce switching count also helps the inverters decrease switching loss. The simulated and experienced results on a cascaded 9-level 3-phase inverter and an F28379D DSP kit have validated the performance of the proposed technique compared with that of the APOD and POD methods.


Author(s):  
Tohid Jalilzadeh ◽  
Mehrdad Tarafdar Hagh ◽  
Mehran Sabahi

PurposeThis paper aims to propose a new transformer-less inverter structure to reduce the common-mode leakage current in grid-connected photovoltaic (PV) systems. Design/methodology/approachThe proposed circuit structure is the same as the conventional full-bridge inverter with three additional power switches in a triangular structure. These three power switches are between the bridge and the output filter, and they mitigate the common-mode leakage current flowing toward the PV panels’ capacitors. The common-mode leakage current mitigation is done through the three-direction clamping cell (TDCC) concept. By clamping the common-mode voltage to the middle voltage of the DC-link capacitors, the leakage current and the total harmonic distortion (THD) of the injected current to the grid is effectively reduced. Therefore, the efficiency is improved. FindingsThe switching modes and the control method are introduced. A comparison is carried out between the proposed structure and other solutions in the literature. The proposed topology and its respective control method are simulated by PSCAD/EMTDC software. The simulation results validate the advantages of the presented structure such as clamping the common-mode voltage and reducing leakage current and THD of injected current to the grid. Originality/valuePresenting a single phase-improved inverter structure with low-leakage current for grid-connected PV power systems represents a significant original contribution to this work. The proposed structure can inject a sinusoidal current with low THD to the AC grid, and the power factor is unity on the AC side. In the half positive cycle, one of the switches in the TDCC is turned off under zero current. Besides, one of the other switches in TDCC is turned on with zero voltage and, therefore, its turn-on switching losses are zero. The efficiency of the proposed topology is high because of the reduction of leakage current and power losses. Accordingly, the presented topology can be a good solution to the leakage current elimination.


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