scholarly journals New Method for Determination of Drain Saturation Voltage in Short Channel MOS Devices Between Liquid Helium to Room Temperature

2001 ◽  
Vol 24 (2) ◽  
pp. 129-134
Author(s):  
Y. Amhouche ◽  
A. El Abbassi ◽  
K. Raïs ◽  
E. Bendada ◽  
R. Rmaily

A new method for drain saturation voltage extraction in submicron MOSFETs is presented. It is based on measurements of the partial derivative of the impact ionization rate. The method has been tested using main of channel length MOSFET devices and compared with others methods.

1979 ◽  
Vol 55 (1) ◽  
pp. 197-202 ◽  
Author(s):  
Z. Dobrovolskis ◽  
W. Hoerstel ◽  
A. Krotkus

2006 ◽  
Vol 527-529 ◽  
pp. 1367-1370
Author(s):  
Lin Zhu ◽  
Peter A. Losee ◽  
T. Paul Chow ◽  
Kenneth A. Jones ◽  
Charles Scozzie ◽  
...  

4H-SiC PiN rectifiers with implanted anode and single-zone JTE were fabricated using AlN capped anneal. The surface damage during the high temperature activation anneal is significantly reduced by using AlN capped anneal. The forward drop of the PiN rectifiers at 100A/cm2 is 3.0V while the leakage current is less than 10-7A/cm2 up to 90% breakdown voltage at room temperature. With 6μm thick and 2×1016cm-3 doped drift layer, the PiN rectifiers can achieve near ideal breakdown voltage up to 1050V. Hole impact ionization rate was extracted and compared with previously reported results.


2020 ◽  
Vol 1004 ◽  
pp. 998-1003
Author(s):  
Jia Xing Wei ◽  
Si Yang Liu ◽  
Sheng Li ◽  
Li Zhi Tang ◽  
Rong Cheng Lou ◽  
...  

The unexpected resistance reduction effect of double-trench SiC MOSFETs under repetitive avalanche stress is investigated in this work. After enduring repetitive avalanche stress, the ON-state drain-source resistance (Rdson) of the device decreases. With the help of TCAD simulations, the dominant mechanism is proved to be the injection of positive charges into the gate trench bottom oxide, which is almost irreversible under zero-voltage bias condition at room temperature. For the injected positive charges attract extra electrons just beneath the gate trench bottom, where the carriers pass through under ON state, the resistivity there is reduced, improving the conduction capability of the device. Moreover, an optimization method is proposed. Since the impact ionization rate (I.I.) and the vertical oxide electric field (E⊥) along the gate trench bottom oxide interface contribute to the injection of positive charges, it is recommended to make the bottom oxide thicker to suppress this effect.


2000 ◽  
Vol 87 (2) ◽  
pp. 781-788 ◽  
Author(s):  
R. Redmer ◽  
J. R. Madureira ◽  
N. Fitzer ◽  
S. M. Goodnick ◽  
W. Schattke ◽  
...  

1995 ◽  
Vol 395 ◽  
Author(s):  
J. Kolnik ◽  
I.H. Oguzman ◽  
K.F. Brennan ◽  
R. Wang ◽  
P.P. Ruden

ABSTRACTIn this paper, we present ensemble Monte Carlo based calculations of electron initiated impact ionization in bulk zincblende GaN using a wavevector dependent formulation of the interband impact ionization transition rate. These are the first reported estimates, either theoretical or experimental, of the impact ionization rates in GaN. The transition rate is determined from Fermi’s golden rule for a two-body screened Coulomb interaction using a numerically determined dielectric function as well as by numerically integrating over all of the possible final states. The Monte Carlo simulator includes the full details of the first four conduction bands derived from an empirical pseudopotential calculation as well as all of the relevant phonon scattering mechanisms. It is found that the ionization rate has a relatively "soft" threshold.


1995 ◽  
Vol 391 ◽  
Author(s):  
S. Saha ◽  
C. S. Yeh ◽  
Ph. Lindorfer ◽  
J. Luo ◽  
U. Nellore ◽  
...  

AbstractThis paper describes an application of process and device simulation programs in the study of substrate current generated by hot-carrier effect in submicron p-channel MOSFET devices. The impact ionization model for holes was calibrated for accurate simulation of substrate current in submicron devices, and an expression for the impact ionization rate of holes in silicon is obtained. The simulated substrate current for 0.57, 0.73 and 1.13 μm devices obtained by the optimized expression agrees very well with the measured data. The optimized impact ionization expression was also used to simulate the effect of p- Lightly Doped Drain impurity profile on substrate current, and the simulated peak substrate current and the corresponding maximum lateral channel electric field as a function of p- dose and length are presented.


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