scholarly journals Post-Mapping Transformations for Low-Power Synthesis

VLSI Design ◽  
1998 ◽  
Vol 7 (3) ◽  
pp. 289-301
Author(s):  
Rajendran Panda ◽  
Farid N. Najm
Keyword(s):  
Power Optimization ◽  
Logic Synthesis ◽  
Transition Density ◽  
Optimization Methods ◽  
Asynchronous Circuits ◽  
Total Power ◽  
Circuit Switching ◽  
Delay Model ◽  
Switching Activity ◽  
Arrival Times

We propose a logic synthesis system that includes power optimization after technology mapping. Our approach is unique in that our post-mapping logic transformations take into account information on circuit delay, capacitance, arrival times, glitches, etc., to provide much better accuracy than previously proposed technology-independent power optimization methods. By changing connections in a mapped circuit, we achieve power improvements up to 13% in case of area- or delay-optimized circuits, with reductions also in area and delay. We show that by applying the proposed technique on circuits that are already restructured for lower switching activity using the technique presented in [11], total power savings up to 59% in case of area-optimized circuits and 38% in case of delay-optimized circuits are achievable. The post-mapping transformations are based on the transition density model of circuit switching activity and the concept of permissible logic functions. The techniques presented here are applicable equally well to both synchronous and asynchronous circuits. The power measurements are done under a general delay model.

scholarly journals Statistical Estimation of the ,Switching Activity in VLSI Circuits

VLSI Design ◽  
1998 ◽  
Vol 7 (3) ◽  
pp. 243-254 ◽  
Author(s):  
Farid N. Najm ◽  
Michael G. Xakellis
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Transition Density ◽  
Absolute Error ◽  
Statistical Simulation ◽  
Vlsi Circuits ◽  
Percentage Error ◽  
Circuit Switching ◽  
Low Density ◽  
Switching Activity

Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these problems are directly related to the extent of circuit switching activity. The average number of transitions per second at a circuit node is a measure of switching activity that has been called the transition density. This paper presents a statistical simulation technique to estimate individual node transition densities in combinational logic circuits. The strength of this approach is that the desired accuracy and confidence can be specified up-front by the user. Another key feature is the classification of nodes into two categories: regular- and low-density nodes. Regular-density nodes are certified with user-specified percentage error and confidence levels. Low-density nodes are certified with an absolute error, with the same confidence. This speeds convergence while sacrificing percentage accuracy only on nodes which contribute little to power dissipation and have few reliability problems.

scholarly journals Logic Synthesis Strategy Oriented to Low Power Optimization

2021 ◽  
Vol 11 (19) ◽  
pp. 8797
Author(s):  
Marcin Kubica ◽  
Adam Opara ◽  
Dariusz Kania
Keyword(s):  
Low Power ◽  
Power Optimization ◽  
Logic Synthesis ◽  
Switching Activity ◽  
Array Type ◽  
Function Decomposition ◽  
Synthesis Strategy ◽  
Combinatorial Circuits ◽  
New Form ◽  
Logic Functions

The article presents a synthesis strategy focused on low power implementations of combinatorial circuits in an array-type FPGA structure. Logic functions are described by means of BDD. A new form of the SWitch activity BDD diagram (SWBDD) is proposed, which enables a function decomposition to minimize the switching activity of circuits. The essence of the proposed idea lies in the proper ordering of the variables and cutting the diagram, ensuring the minimization of switching in the combination circuit. This article contains the results of experiments confirming the effectiveness of the developed concept of decomposition. They were performed on popular benchmarks using academic and commercial synthesis systems.

scholarly journals Fast Atom Search Algorithm for Reactive Power Optimization of Power Grid with High-Penetration Wind and Solar Energies

2020 ◽  
Vol 2020 ◽  
pp. 1-15
Author(s):  
Fang Zeng ◽  
Hongchun Shu
Keyword(s):  
Reactive Power ◽  
Power Optimization ◽  
Search Algorithm ◽  
Power Grid ◽  
Wind Farms ◽  
Solar Irradiation ◽  
Total Power ◽  
Reactive Power Optimization ◽  
Search Optimization ◽  
High Penetration

This paper constructs a reliable reactive power optimization (RPO) model of power grid with the controlled participation of high-penetration wind and solar energies and provides a novel fast atom search optimization (FASO) algorithm to reach a set of solutions to the RPO problem. The developed FASO algorithm owns prominent merits of high searching efficiency and premature convergence avoidance compared with the original atom search optimization (ASO) algorithm, which is applied to determine the optimal dispatch scheme including terminal voltage of generators, the capacity of static VAR compensator (SVC), reactive power output of wind and solar energies, and the tap ratio of transformers. There are two objective functions to be minimized for maintaining the safe and reliable operation of power grid, i.e., total power loss of transmission lines and total voltage deviation of nodes. Meanwhile, the regulation capacities of wind farms and photovoltaic (PV) stations are evaluated based on different weather conditions, i.e., wind speed and solar irradiation. Particularly, the reactive power outputs of wind and solar energies can be globally controlled to coordinate with other controllable units instead of a local self-control. Eventually, the extended IEEE 9-bus and IEEE 39-bus systems are introduced to test the performance of the FASO algorithm for RPO problem. It has been verified that FASO can not only meet the optimal regulation requirements of RPO but also obtain high-quality regulation schemes with the fastest convergence speed and highest convergence stability in contrast with else algorithms.

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