scholarly journals Statistical Estimation of the ,Switching Activity in VLSI Circuits

VLSI Design ◽  
1998 ◽  
Vol 7 (3) ◽  
pp. 243-254 ◽  
Author(s):  
Farid N. Najm ◽  
Michael G. Xakellis
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Transition Density ◽  
Absolute Error ◽  
Statistical Simulation ◽  
Vlsi Circuits ◽  
Percentage Error ◽  
Circuit Switching ◽  
Low Density ◽  
Switching Activity

Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these problems are directly related to the extent of circuit switching activity. The average number of transitions per second at a circuit node is a measure of switching activity that has been called the transition density. This paper presents a statistical simulation technique to estimate individual node transition densities in combinational logic circuits. The strength of this approach is that the desired accuracy and confidence can be specified up-front by the user. Another key feature is the classification of nodes into two categories: regular- and low-density nodes. Regular-density nodes are certified with user-specified percentage error and confidence levels. Low-density nodes are certified with an absolute error, with the same confidence. This speeds convergence while sacrificing percentage accuracy only on nodes which contribute little to power dissipation and have few reliability problems.

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

2015 ◽  
Vol 24 (07) ◽  
pp. 1550094 ◽  
Author(s):  
Jizhong Shen ◽  
Liang Geng ◽  
Xuexiang Wu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Clock Cycle ◽  
Control Technique ◽  
Switching Activity ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Deep Impact ◽  
Power Pulse

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

scholarly journals 4-bit Carry Look Ahead Adder Using MGDI Technique

2021 ◽  
Vol 9 (9) ◽  
pp. 855-860
Author(s):  
Shaik Mahammad Ameer Afridi
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Power Dissipation ◽  
High Performance ◽  
Digital Signal ◽  
Vlsi Circuits ◽  
Digital Vlsi ◽  
Look Ahead ◽  
Energy Trade ◽  
Integral Role

Abstract: Today's high-performance processor is built with arithmetic logic units that add and subtract key components. Design considerations related to low power and high performance digital VLSI circuits have become more prevalent in today's world. In order to develop low-power and high-performance processors, the designers need to design their adder circuits with the required speed and power dissipation for their applications. This topic introduces the concept of a adder using MGDI Technique. The Exact Speculative Carry Look Ahead Adder the use of the Modified-GDI (Modified-Gate Diffusion Input) is cautioned in this work. The delay, location and energy trade off performs a integral role in VLSI. We already comprehend that designs which are of CMOS fashion occupy extra area might also eat extra strength consumption. The switching conduct of the circuit reason the heating up of integrated circuits affects the working stipulations of the purposeful unit. The adders are the most important parts of countless applications such as microprocessors, microcontrollers and digital signal processors and additionally in actual time applications. Hence it is necessary to minimize the adder blocks to format a perfect processor. This work is proposed on a 16 bit carry seem to be in advance adder is designed through using MGDI gate and 4T XOR gates and a speculator blocks. The proposed MGDI raise Look Ahead adder occupies 68% much less region and the strength consumption and the propagation extend additionally considerably reduces when in contrast to the traditional carry Look Ahead adder why because the variety transistors extensively reduces from 1448 (Conventional) to 456 (Proposed CLA). The simulation consequences of the proposed format carried out in Xilinx. Keywords: Delay, power dissipation, voltage, transistor sizing.

scholarly journals Power Efficient VLSI Inverter Design using Adiabatic Logic and Estimation of Power dissipation using VLSI-EDA Tool

2012 ◽  
pp. 155-158
Author(s):  
Samik Samanta
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Vlsi Circuits ◽  
Limiting Factor ◽  
Switching Activity ◽  
Cmos Inverter ◽  
Power Efficient ◽  
Adiabatic Switching ◽  
Adiabatic Logic ◽  
Innovative Solutions

Power dissipation becoming a limiting factor in VLSI circuits and systems. Due to relatively high complexity of VLSI systems used in various applications, the power dissipation in CMOS inverter, arises from it’s switching activity, which is mainly influenced by the supply voltage and effective capacitance.[1,2,3] To optimize power dissipation, the researches show various techniques like appropriate coding, appropriate design architectures, appropriate manipulation algorithms. In this paper we have applied adiabatic logic design approach to design COMS inverter. Adiabatic switching techniques based on energy recovery principle are one of the innovative solutions at a circuit and logic level achieve reduction in power [12] Various adiabatic logic based inverters are shown. Mainly our aim is to design and simulate PFAL inverters. Finally we have calculated dissipated power of static CMOS inverter and compare it with that of PFAL based inverter. [4, 6]

POWER REDUCTION TECHNIQUE USING MULTIPLE SUPPLY VOLTAGE AND SWITCHING ACTIVITY ANALYSIS

2013 ◽  
Vol 22 (02) ◽  
pp. 1250079
Author(s):  
BASHAR HADDAD ◽  
AMIN JARRAH
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Critical Path ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Activity Analysis ◽  
Vlsi Circuits ◽  
Total Power ◽  
Switching Activity ◽  
Activity Factor

Recent demand for low power VLSI circuits has been pushing the development of innovative approaches to reduce power dissipation. Supply voltage (V CC ) and switching activity factor (α) are main sources of dynamic power dissipation in CMOS technology. Furthermore, the power dissipation increases exponentially by the value of supply voltage. New approach based on switching activity analysis and multiple supply voltage is implemented successfully in logical circuits, taking in mind the critical path(s) of the design and switching activity factor of each element in the design. High supply voltage is applied on elements on the critical path(s). Elements off the critical path(s) are classified into categories according to their switching activity factors. The total power dissipation is reduced, while the propagation delay remains without any increase. The proposed approach combines the concepts of critical/non-critical paths and switching activity analysis to assign different V CCs to different elements.

scholarly journals Post-Mapping Transformations for Low-Power Synthesis

VLSI Design ◽  
1998 ◽  
Vol 7 (3) ◽  
pp. 289-301
Author(s):  
Rajendran Panda ◽  
Farid N. Najm
Keyword(s):  
Power Optimization ◽  
Logic Synthesis ◽  
Transition Density ◽  
Optimization Methods ◽  
Asynchronous Circuits ◽  
Total Power ◽  
Circuit Switching ◽  
Delay Model ◽  
Switching Activity ◽  
Arrival Times

We propose a logic synthesis system that includes power optimization after technology mapping. Our approach is unique in that our post-mapping logic transformations take into account information on circuit delay, capacitance, arrival times, glitches, etc., to provide much better accuracy than previously proposed technology-independent power optimization methods. By changing connections in a mapped circuit, we achieve power improvements up to 13% in case of area- or delay-optimized circuits, with reductions also in area and delay. We show that by applying the proposed technique on circuits that are already restructured for lower switching activity using the technique presented in [11], total power savings up to 59% in case of area-optimized circuits and 38% in case of delay-optimized circuits are achievable. The post-mapping transformations are based on the transition density model of circuit switching activity and the concept of permissible logic functions. The techniques presented here are applicable equally well to both synchronous and asynchronous circuits. The power measurements are done under a general delay model.

Electrothermal analysis of integrated circuits: a realization by infrared thermography

2021 ◽  
Author(s):  
Farnoos Farrokhi
Keyword(s):  
Temperature Distribution ◽  
Integrated Circuits ◽  
Power Dissipation ◽  
Electronic Device ◽  
Power Measurement ◽  
Device Under Test ◽  
Distribution Analysis ◽  
Ir Thermography ◽  
Temperature Dependent ◽  
Run Time

The International Technology Roadmap for Silicon (ITRS) predicted that by the year 2016, a high-performance chip could dissipate as much as 300 W/cm² of heat. Another more noticeable thermal issue in IC's is the uneven temperature distribution. Increased power dissipation and greater temperature variation highlight the need for electrothermal analysis of electronic components. The goal of this research is to develop an experimental infrared measurement technique for the thermal and electrothermal analysis of electronic circuits. The objective of the electrothermal analysis is to represent the behavior of the temperature dependent characteristics of electronic device in near real work condition. An infrared (IR) thermography setup to perform the temperature distribution analysis and power dissipation measurement of the device under test is proposed in this reasearch. The system is based on a transparent oil heatsink which captures the thermal profile and run-time power dissipation from the device under test with a very fine degree of granularity. The proposed setup is used to perform the thermal analysis and power measurement of an Intel Dual Core E2180 processor. The power dissipation of the processor is obtained by calculating and measuring the heat transfer coefficient of the oil heatsink. Moreover, the power consumption of the processor is measured by isolating the current used by the CPU at run time. A three-dimensional fininte element thermal model is developed to simulate the thermal properties of the processor. The results obtained using this simulation is compared to the experimental results from IR thermography. A methodology to perform electrothermal analysis on integrated circuits is introduced. This method is based on coupling a standard electrical simulator, which is often used in the design process, and IR thermography system through an efficient interface program. The proposed method is capable of updating the temperature dependent parameters of device in near real time. The proposed method is applied to perform electrothermal analysis of a power MOSFET to measure the temperature distribution and the device performance. The DC characteristics of the device are investigated. The obtained results indicated that the operating point, I-V characteristics and power dissipation of the MOSFET vary significantly with temperature.

scholarly journals Novel Spatiotemporal Feature Extraction Parallel Deep Neural Network for Forecasting Confirmed Cases of Coronavirus Disease 2019

2020 ◽  
Author(s):  
Chiou-Jye Huang ◽  
Yamin Shen ◽  
Ping-Huan Kuo ◽  
Yung-Hsiang Chen
Keyword(s):  
Neural Network ◽  
Deep Neural Network ◽  
Absolute Error ◽  
Mean Absolute Percentage Error ◽  
The Other ◽  
Percentage Error ◽  
Model Assessment ◽  
Absolute Percentage Error ◽  
Spatiotemporal Feature ◽  
The Mean

AbstractThe coronavirus disease 2019 pandemic continues as of March 26 and spread to Europe on approximately February 24. A report from April 29 revealed 1.26 million confirmed cases and 125 928 deaths in Europe. This study proposed a novel deep neural network framework, COVID-19Net, which parallelly combines a convolutional neural network (CNN) and bidirectional gated recurrent units (GRUs). Three European countries with severe outbreaks were studied—Germany, Italy, and Spain—to extract spatiotemporal feature and predict the number of confirmed cases. The prediction results acquired from COVID-19Net were compared to those obtained using a CNN, GRU, and CNN-GRU. The mean absolute error, mean absolute percentage error, and root mean square error, which are commonly used model assessment indices, were used to compare the accuracy of the models. The results verified that COVID-19Net was notably more accurate than the other models. The mean absolute percentage error generated by COVID-19Net was 1.447 for Germany, 1.801 for Italy, and 2.828 for Spain, which were considerably lower than those of the other models. This indicated that the proposed framework can accurately predict the accumulated number of confirmed cases in the three countries and serve as a crucial reference for devising public health strategies.

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