Efficient switching activity simulation under a real delay model using a bitparallel approach

Author(s):  
M. Buhler ◽  
M. Papesch ◽  
K. Kapp ◽  
U.G. Baitinger
VLSI Design ◽  
2001 ◽  
Vol 12 (1) ◽  
pp. 69-79
Author(s):  
G. Theodoridis ◽  
S. Theoharis ◽  
D. Soudris ◽  
C. Goutis

Our aim is the development of a novel probabilistic method to estimate the power consumption of a combinational circuit under real gate delay model handling temporal, structural and input pattern dependencies. The chosen gate delay model allows handling both the functional and spurious transitions. It is proved that the switching activity evaluation problem assuming real gate delay model is reduced to the zero delay switching activity evaluation problem at specific time instances. A modified Boolean function, which describes the logic behavior of a signal at any time instance, including time parameter is introduced. Moreover, a mathematical model based on Markov stochastic processes, which describes the temporal and spatial correlation in terms of the associated zero delay based parameters is presented. Based on the mathematical model and considering the modified Boolean function, a new algorithm to evaluate the switching activity at specific time instances using Ordering Binary Decision Diagrams (OBBDs) is also presented. Comparative study of benchmark circuits demonstrates the accuracy and efficiency of the proposed method.


VLSI Design ◽  
1998 ◽  
Vol 7 (3) ◽  
pp. 289-301
Author(s):  
Rajendran Panda ◽  
Farid N. Najm

We propose a logic synthesis system that includes power optimization after technology mapping. Our approach is unique in that our post-mapping logic transformations take into account information on circuit delay, capacitance, arrival times, glitches, etc., to provide much better accuracy than previously proposed technology-independent power optimization methods. By changing connections in a mapped circuit, we achieve power improvements up to 13% in case of area- or delay-optimized circuits, with reductions also in area and delay. We show that by applying the proposed technique on circuits that are already restructured for lower switching activity using the technique presented in [11], total power savings up to 59% in case of area-optimized circuits and 38% in case of delay-optimized circuits are achievable. The post-mapping transformations are based on the transition density model of circuit switching activity and the concept of permissible logic functions. The techniques presented here are applicable equally well to both synchronous and asynchronous circuits. The power measurements are done under a general delay model.


1999 ◽  
Author(s):  
Li-Shiuan Peh ◽  
William J. Dally
Keyword(s):  

Filomat ◽  
2017 ◽  
Vol 31 (16) ◽  
pp. 5271-5293
Author(s):  
A.K. Pal ◽  
P. Dolai ◽  
G.P. Samanta

In this paper we have studied the dynamical behaviours of a delayed two-species competitive system affected by toxicant with imprecise biological parameters. We have proposed a method to handle these imprecise parameters by using parametric form of interval numbers. We have discussed the existence of various equilibrium points and stability of the system at these equilibrium points. In case of toxic stimulatory system, the delay model exhibits a stable limit cycle oscillation. Computer simulations are carried out to illustrate our analytical findings.


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