Capacitance-Voltage and Interface State Density Characteristics of GaAs and In0.53Ga0.47As MOS Capacitors Incorporating a PECVD Si3N4 Dielectric

2019 ◽  
Vol 35 (3) ◽  
pp. 415-430 ◽  
Author(s):  
Eamon O'Connor ◽  
Vladimir Djara ◽  
Scott Monaghan ◽  
Paul Hurley ◽  
Karim Cherkaoui
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Capacitance Voltage

The Correlation between the Reduction of Interface State Density at the SiO2/SiC Interface and the NO Post-Oxide-Annealing Conditions

2019 ◽  
Vol 954 ◽  
pp. 104-108
Author(s):  
Heng Yu Xu ◽  
Cai Ping Wan ◽  
Jin Ping Ao
Keyword(s):  
Mass Spectrometry ◽  
Secondary Ion Mass Spectrometry ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Annealing Conditions ◽  
N Concentration ◽  
Higher Temperature ◽  
Secondary Ion

We fabricated SiO2/4H-SiC (0001) MOS capacitors with oxidation temperature at 1350°C, followed by post-oxide-annealing (POA) in NO simply by the control of POA temperatures and times. A correlation between the reduction of interface state density and the increasing of N concentration at the interface has been indicated by C-ψs measurement and secondary ion mass spectrometry (SIMS). The SiO2/4H-SiC interface density decreased when POA temperature was elevated, and the sample annealed at 1300°C for 30min showed the lowest interface state density about 1.5×1012 cm-2eV-1 at Ec-E=0.3 eV when the N concentration is 11.5×1020 cm-3. Meanwhile, the SiO2 /4H-SiC interface annealed at 1200°C for 120min showed the highest N concentration at the 4H-SiC/SiO2 interface is 12.5×1020 cm-3, whereas the interface state density is 2.5×1012 cm-2eV-1 at Ec-E=0.3 eV higher than 1300°C for 30min. The results suggested that higher temperature POA might be much more efficiency in decreased the 4H-SiC MOS interface density with increasing the N area concentration.

Processing and Characterization of MOS Capacitors Fabricated on 2°-Off Axis 4H-SiC Epilayers

2016 ◽  
Vol 858 ◽  
pp. 663-666
Author(s):  
Marilena Vivona ◽  
Patrick Fiorenza ◽  
Tomasz Sledziewski ◽  
Alexandra Gkanatsiou ◽  
Michael Krieger ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Interface State ◽  
State Density ◽  
Metal Oxide Semiconductor ◽  
Interface State Density ◽  
Device Fabrication ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Oxide Breakdown

In this work, the electrical properties of SiO2/SiC interfaces onto a 2°-off axis 4H-SiC layer were studied and validated through the processing and characterization of metal-oxide-semiconductor (MOS) capacitors. The electrical analyses on the MOS capacitors gave an interface state density in the low 1×1012 eV-1cm-2 range, which results comparable to the standard 4°-off-axis 4H-SiC, currently used for device fabrication. From Fowler-Nordheim analysis and breakdown measurements, a barrier height of 2.9 eV and an oxide breakdown of 10.3 MV/cm were determined. The results demonstrate the maturity of the 2°-off axis material and pave the way for the fabrication of 4H-SiC MOSFET devices on this misorientation angle.

Electrical Properties of High-K LaLuO3 Gate Oxide for SOI MOSFETs

2011 ◽  
Vol 276 ◽  
pp. 87-93
Author(s):  
Y.Y. Gomeniuk ◽  
Y.V. Gomeniuk ◽  
A. Nazarov ◽  
P.K. Hurley ◽  
Karim Cherkaoui ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Interface State ◽  
Channel Length ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Threshold Voltages

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.

In-Situ Etch to Improve Chemical Beam Epitaxy Regrown AlgaAs/GaAs Interfaces for HBT Applications

1996 ◽  
Vol 448 ◽  
Author(s):  
Y.M. Hsin ◽  
N. Y. Li ◽  
C. W. Tu ◽  
P. M. Asbeck
Keyword(s):  
Etching Rate ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Chemical Beam Epitaxy ◽  
Capacitance Voltage ◽  
Substrate Temperatures ◽  
Etching Effect

AbstractWe have studied the etching effect of AlxGa1-xAs (0≤ x ≤ 0.5) by trisdimethylaminoarsenic (TDMAAs) at different substrate temperatures, and the quality of the resulting etched/regrown GaAs interface. We find that the etching rate of AlxGa1-x As decreases with increasing Al composition, and the interface trap density of the TDMAAs etched/regrown interface can be reduced by about a factor of 10 as deduced from capacitance-voltage carrier profiles. A smooth surface morphology of GaAs with an interface state density of 1.4×l011 cm−2 can be obtained at a lower in-situ etching temperature of 550°C. Moreover, by using this in-situ etching the I-V characteristics of regrown p-n junctions of Al0.35Ga0.65As/Al0.25Ga0.75As and Al0.35Ga0.65As/GaAs can be improved.

Enhanced Channel Mobility in 4H-SiC MISFETs by Utilizing Deposited SiN/SiO2 Stack Gate Structures

2008 ◽  
Vol 600-603 ◽  
pp. 679-682 ◽  
Author(s):  
Masato Noborio ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Post Deposition Annealing ◽  
Interface Quality ◽  
Channel Mobility ◽  
Capacitance Voltage ◽  
Mis Capacitors ◽  
Post Deposition ◽  
Time Lead

Deposited SiN/SiO2 stack gate structures have been investigated to improve the 4H-SiC MOS interface quality. Capacitance-voltage measurements on fabricated SiN/SiO2 stack gate MIS capacitors have indicated that the interface state density is reduced by post-deposition annealing in N2O at 1300°C. The usage of thin SiN and increase in N2O-annealing time lead to a low interface state density of 1×1011 cm-2eV-1 at EC – 0.2 eV. Oxidation of the SiN during N2O annealing has resulted in improvement of SiC MIS interface. The fabricated SiN/SiO2 stack gate MISFETs demonstrate a high channel mobility of 32 cm2/Vs on (0001)Si face and 40 cm2/Vs on (000-1)C face.

Synergistic effects in MOS capacitors with an Au/HfO2-SiO2/Si structure irradiated with neutron and gamma ray

2021 ◽  
Author(s):  
Jianmin Shi ◽  
Xinwei Wang ◽  
Xiuyu Zhang ◽  
Jianming Xue ◽  
Xun Guo ◽  
...  
Keyword(s):  
Synergistic Effect ◽  
Energy Loss ◽  
Gamma Irradiation ◽  
Ionization Energy ◽  
Energy Deposition ◽  
Gamma Ray ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors

Abstract The properties of oxide trapped charges and interface state density in the metal oxide semiconductor (MOS) capacitors with an Au/HfO2-SiO2/Si structure were investigated under irradiation of 14 MeV neutron and 60Co gamma-ray. In the mixed neutron and gamma irradiation environment, the formation of the oxide trapped charges in the HfO2-SiO2 layer is determined by the total deposited ionization energy, i.e. the sum of ionization energy deposition of the neutrons and the accompanying gamma rays, while the influence of the displacement damage caused by 14 MeV neutrons can be ignored. The interface state density depends not only on the ionizing energy loss (IEL) but also the non-ionizing energy loss (NIEL), and NIEL plays a major role below the critical neutron fluence of 4.5×1012 n/cm2. The synergistic effect of the interface state is observed increases with energy deposition in the oxide at lower fluences, while decreasing above the critical fluence. These results confirm the existence of the synergistic effect of neutron and gamma irradiation in damaging HfO2 MOS devices.

Correlation between Field Effect Mobility and Accumulation Conductance at 4H-SiC MOS Interface with Barium

2018 ◽  
Vol 924 ◽  
pp. 477-481
Author(s):  
Kosuke Muraoka ◽  
Seiji Ishikawa ◽  
Hiroshi Sezaki ◽  
Tomonori Maeda ◽  
Shinichiro Kuroki
Keyword(s):  
Linear Correlation ◽  
Field Effect ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Field Effect Mobility ◽  
Mos Capacitors

A correlation between field effect mobility and an accumulation conductance has been investigated at 4H-SiC MOS interface with barium. 4H-SiC n-channel MOSFETs and n-type MOS capacitors were fabricated with a barium-introduced SiO2and a conventional dry SiO2. The field effect mobility was enhanced by introducing the barium-introduced SiO2. It is found that there is a linear correlation between the mobility and the accumulation conductance. The MOS interface of the barium-introduced SiO2had a lower interface state density of 2×1011cm-2eV-1than that of the conventional dry SiO2.

Electrical Properties Evaluation on High Quality Hetero-Epitaxial 3C-SiC(001) for MOSFET Applications

2015 ◽  
Vol 821-823 ◽  
pp. 773-776 ◽  
Author(s):  
Ruggero Anzalone ◽  
Stefania Privitera ◽  
Alessandra Alberti ◽  
Nicolo’ Piluso ◽  
Patrick Fiorenza ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Electrical Conductance ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Crystalline Quality ◽  
X Ray Diffraction ◽  
Mos Capacitors ◽  
Afm Analysis ◽  
The Relationship

The effect of the crystal quality and surface morphology on the electrical properties of MOS capacitors has been studied in devices manufactured on 3C-SiC epitaxial layers grown on Silicon (100) substrate. The interface state density, which represents one of the most important parameters for the 3C-SiC MOSFET development, has been determined through capacitance measurements. A cross-correlation between High Resolution X-ray Diffraction, AFM analysis and electrical conductance measurements has allowed determining the relationship between the crystalline quality and the interface state density. By improving the crystalline quality, a decrease of the interface state density down to 1010cm-2eV-1was observed.

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