Effect of In Situ Hydrogen Annealing on Dielectric Property of a Low Temperature Silicon Nitride Layer in a Bottom-Gate Nanocrystalline Silicon TFT by Catalytic CVD

2019 ◽  
Vol 28 (1) ◽  
pp. 395-399 ◽  
Author(s):  
Youn-Jin Lee ◽  
Kyoung-Min Lee ◽  
Jae-Dam Hwang ◽  
Kil-Sun No ◽  
Wan-Shick Hong
2019 ◽  
Vol 25 (3) ◽  
pp. 259-262
Author(s):  
Youn-Jin Lee ◽  
Kyoung-Min Lee ◽  
Jae-Dam Hwang ◽  
Kil-Sun No ◽  
Kap Soo Yoon ◽  
...  

Author(s):  
Younan Hua ◽  
Bingsheng Khoo ◽  
Henry Leong ◽  
Yixin Chen ◽  
Eason Chan ◽  
...  

Abstract In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.


1988 ◽  
Vol 43 (3) ◽  
pp. 293-301 ◽  
Author(s):  
Eiichi Tamiya ◽  
Masao Gotoh ◽  
Tomoko Matsui ◽  
Masayuki Tanaka ◽  
Isao Karube

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