Impact of Gate Dielectric Breakdown Induced Microstructural Defects on Transistor Reliability

2019 ◽  
Vol 22 (1) ◽  
pp. 11-25 ◽  
Author(s):  
Xiang Li ◽  
Kin Leong Pey ◽  
Vui Lip Lo ◽  
Rakesh Ranjan ◽  
Chih Hang Tung ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Microstructural Defects ◽  
Transistor Reliability

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

FDSOI Mosfet gate dielectric breakdown Vd dependancy

2018 ◽  
Author(s):  
Xavier Federspiel ◽  
Mustapha Rafik ◽  
Melissa Arabi ◽  
Antoine Cros ◽  
Florian Cacho
Keyword(s):  
Gate Dielectric ◽  
Dielectric Breakdown

Electron-Beam-Induced Current Study of Breakdown Behavior of High-K Gate MOSFETs

2009 ◽  
Vol 156-158 ◽  
pp. 461-466
Author(s):  
Jun Chen ◽  
Takashi Sekiguchi ◽  
Masami Takase ◽  
Naoki Fukata ◽  
Ryu Hasunuma ◽  
...  
Keyword(s):  
Electron Beam ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Microscopic Investigation ◽  
Oxide Semiconductor ◽  
Induced Current ◽  
Electrical Stress ◽  
High K ◽  
Electron Beam Induced Current ◽  
Induced Defects

We report a dynamic and microscopic investigation of electrical stress induced defects in metal-oxide-semiconductor (MOS) devices with high-k gate dielectric by using electron-beam induced current (EBIC) technique. The correlation between time-dependent dielectric breakdown (TDDB) characteristics and EBIC imaging of breakdown sites are found. A systematic study was performed on pre-existing and electrical stress induced defects. Stress-induced defects are related to the formation of electron trapping defects. The origin of pre-existing defects is also discussed in terms of oxygen vacancy model with comparing different gate electrodes.

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