Simulation of Retention Characteristics for Metal Nanocrystal Nonvolatile Memory with a Modified Direct Tunneling Model

2019 ◽  
Vol 18 (1) ◽  
pp. 141-148
Author(s):  
Yingtao Li ◽  
Ming Liu ◽  
Shibing Long ◽  
Qin Wang ◽  
Qi Liu ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
Tunneling Model ◽  
Direct Tunneling ◽  
Retention Characteristics

Charge storage and data retention characteristics of forming gas-annealed Gd2O3-nanocrystal nonvolatile memory cell

2012 ◽  
Vol 52 (8) ◽  
pp. 1627-1631 ◽  
Author(s):  
Jer-Chyi Wang ◽  
Chih-Ting Lin ◽  
Chi-Hsien Huang ◽  
Chao-Sung Lai ◽  
Chin-Hsiang Liao
Keyword(s):  
Nonvolatile Memory ◽  
Memory Cell ◽  
Charge Storage ◽  
Data Retention ◽  
Retention Characteristics

Modified ITAT Model for Data Retention in Nanocrystals Based Flash Memory Gate Stack

2017 ◽  
Vol 45 ◽  
pp. 1-11
Author(s):  
Rasika Dhavse ◽  
Kumar Prashant ◽  
Chetan Dabhi ◽  
Anand Darji ◽  
R.M. Patrikar
Keyword(s):  
Flash Memory ◽  
Low Voltage ◽  
Flat Band ◽  
Data Retention ◽  
Gate Stack ◽  
Tunneling Model ◽  
Idle Mode ◽  
Direct Tunneling ◽  
Device Lifetime ◽  
P Type

This work applies combination of Direct Tunneling model and BSIM4 based ITAT model to explain the leakage of electrons from charged nanocrystals to p-type silicon substrate in data retention condition, for an ultra-thin tunnel oxide, low voltage programmable silicon nanocrystal based flash gate stack. Basic expressions of these models are modified to incorporate the nanocrystals related charge leakage in idle mode. The concept is supported by simulating these models and comparing them with the experimental data. Transition of electrons is considered as a result of Direct Tunneling and their trapping de-trapping via water related hydrogen traps. However, it is found that modified ITAT mechanism is the dominant one. Flat-band voltage shift profile fits accurately with the model with an extrapolated 10 years device lifetime without memory closure. 3 nm thick tunnel oxide and 100 nm sized nanocrystal fabrication with Electron Beam Lithography are main features of the devices.

Charge Storage Characteristics of Si-Rich Silicon Nitride and the Effect of Tunneling Thickness on Nonvolatile Memory Performance

2011 ◽  
Vol 181-182 ◽  
pp. 307-311
Author(s):  
Hong Hanh Nguyen ◽  
Ngoc Son Dang ◽  
Van Duy Nguyen ◽  
Kyungsoo Jang ◽  
Kyunghyun Baek ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Nonvolatile Memory ◽  
Memory Performance ◽  
Charge Trapping ◽  
Oxide Thickness ◽  
Memory Window ◽  
Charge Storage ◽  
Operating Voltage ◽  
Silicon Clusters ◽  
Retention Characteristics

Nonvolatile memory (NVM) devices with nitride-nitride-oxynitride (NNO) stack structure using Si-rich silicon nitride (SiNx) as charge trapping layer on glass substrate were fabricated. Amorphous silicon clusters existing in the Si-rich SiNxlayer enhance the charge storage capacity of the devices. Low temperature poly-silicon (LTPS) technology, plasma-assisted oxidation/nitridation method to form a uniform ultra-thin tunneling layer, and an optimal Si-rich SiNxcharge trapping layer were used to fabricate NNO NVM devices with different tunneling thickness 2.3, 2.6 and 2.9 nm. The increase memory window, lower voltage operation but little scarifying in retention characteristics of nitride trap NVM devices had been accomplished by reducing the tunnel oxide thickness. The fabricated NVM devices with 2.9 nm tunneling thickness shows excellent electrical properties, such as a low threshold voltage, a high ON/OFF current ratio, a low operating voltage of less than ±9 V and a large memory window of 2.7 V, which remained greater than 72% over a period of 10 years.

scholarly journals Strong molecular weight effects of gate-insulating memory polymers in low-voltage organic nonvolatile memory transistors with outstanding retention characteristics

2016 ◽  
Vol 8 (1) ◽  
pp. e235-e235 ◽  
Author(s):  
Jooyeok Seo ◽  
Sungho Nam ◽  
Hwajeong Kim ◽  
Thomas D Anthopoulos ◽  
Donal D C Bradley ◽  
...  
Keyword(s):  
Molecular Weight ◽  
Nonvolatile Memory ◽  
Low Voltage ◽  
Retention Characteristics

Electrical Characterization of a Double Barrier Direct Tunneling Diode Structure

1999 ◽  
Vol 567 ◽  
Author(s):  
E. M. Dons ◽  
C. S. Skowronski ◽  
K. R. Farmer
Keyword(s):  
Nonvolatile Memory ◽  
Electrical Characterization ◽  
Diode Structure ◽  
Electrical Measurements ◽  
Si Substrates ◽  
Direct Tunneling ◽  
Tunneling Diode ◽  
Nonvolatile Memory Devices ◽  
Interface Potential

ABSTRACTWe report the electrical characterization of a direct tunneling diode structure that incorporates a multilayer dielectric. The dielectric consists of a stack of two thermally grown, ultrathin SiO2 layers, each ∼3.5 rin thick, separated by a deposited, continuous, undoped, ultrathin nanocrystalline Si layer ∼5.0 nm thick. Electrical measurements of this structure are reported for both n-type and p-type Si substrates. We find that the room temperature transport through this structure is accounted for by describing the intermediate Si layer as a quantum well with a continuum of states, and by otherwise assuming bulk properties for the ultrathin layers, such as the existence of a bandgap in the Si well and the usual Si-SiO2 interface potential barrier height at all interfaces. This structure is expected to be useful as the active dielectric in nonvolatile memory devices.

Impact of oxygen incorporation at the Si3N4∕Al2O3 interface on retention characteristics for nonvolatile memory applications

2008 ◽  
Vol 93 (2) ◽  
pp. 022101 ◽  
Author(s):  
Man Chang ◽  
Yongkyu Ju ◽  
Joonmyoung Lee ◽  
Seungjae Jung ◽  
Hyejung Choi ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
Oxygen Incorporation ◽  
Retention Characteristics ◽  
Memory Applications

Collective Tunneling Model in Charge-Trap-Type Nonvolatile Memory Cell

2011 ◽  
Vol 50 (4) ◽  
pp. 04DD04 ◽  
Author(s):  
Masakazu Muraguchi ◽  
Yoko Sakurai ◽  
Yukihiro Takada ◽  
Yasuteru Shigeta ◽  
Mitsuhisa Ikeda ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
Memory Cell ◽  
Tunneling Model ◽  
Charge Trap

Performance enhancement of TiSi2 coated Si nanocrystal memory device

2009 ◽  
Vol 1160 ◽  
Author(s):  
Huimei Zhou ◽  
Jianlin Liu
Keyword(s):  
Nonvolatile Memory ◽  
Storage Capacity ◽  
Performance Enhancement ◽  
Memory Device ◽  
Charge Storage ◽  
Si Nanocrystal ◽  
Device Applications ◽  
Retention Characteristics ◽  
Cmos Compatible ◽  
Nanocrystal Memory

AbstractSelf-aligned TiSi2 coated Si nanocrystal nonvolatile memory is fabricated. This kind of MOSFET memory device is not only thermally stable, but also shows better performance in charge storage capacity, writing, erasing speed and retention characteristics. This indicates that CMOS compatible silicidation process to fabricate TiSi2 coated Si nanocrystal memory is promising in memory device applications.

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