scholarly journals Strong molecular weight effects of gate-insulating memory polymers in low-voltage organic nonvolatile memory transistors with outstanding retention characteristics

2016 ◽  
Vol 8 (1) ◽  
pp. e235-e235 ◽  
Author(s):  
Jooyeok Seo ◽  
Sungho Nam ◽  
Hwajeong Kim ◽  
Thomas D Anthopoulos ◽  
Donal D C Bradley ◽  
...  
Keyword(s):  
Molecular Weight ◽  
Nonvolatile Memory ◽  
Low Voltage ◽  
Retention Characteristics

Ionic nanocluster-evolved polymers for low-voltage flexible organic nonvolatile memory transistors

2019 ◽  
Vol 6 (9) ◽  
pp. 1899-1904
Author(s):  
Chulyeon Lee ◽  
Jaehoon Jeong ◽  
Hwajeong Kim ◽  
Youngkyoo Kim
Keyword(s):  
Nonvolatile Memory ◽  
Low Voltage ◽  
Retention Characteristics

The ionic nanocluster-evolved PAMPSA–AN layers enable nonvolatile memory OFETs to be operated at low voltages with outstanding retention characteristics.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Charge storage and data retention characteristics of forming gas-annealed Gd2O3-nanocrystal nonvolatile memory cell

2012 ◽  
Vol 52 (8) ◽  
pp. 1627-1631 ◽  
Author(s):  
Jer-Chyi Wang ◽  
Chih-Ting Lin ◽  
Chi-Hsien Huang ◽  
Chao-Sung Lai ◽  
Chin-Hsiang Liao
Keyword(s):  
Nonvolatile Memory ◽  
Memory Cell ◽  
Charge Storage ◽  
Data Retention ◽  
Retention Characteristics

Low-voltage electro-optical memory device based on NiO nanorods dispersed in a ferroelectric liquid crystal

RSC Advances ◽  
2016 ◽  
Vol 6 (59) ◽  
pp. 53873-53881 ◽  
Author(s):  
Achu Chandran ◽  
Jai Prakash ◽  
Jitendra Gangwar ◽  
Tilak Joshi ◽  
Avanish Kumar Srivastava ◽  
...  
Keyword(s):  
Liquid Crystal ◽  
Low Power ◽  
Nickel Oxide ◽  
Nonvolatile Memory ◽  
Low Voltage ◽  
Optical Memory ◽  
Memory Device ◽  
Ferroelectric Liquid Crystal ◽  
Oxide Nanorods ◽  
Nonvolatile Memory Device

A low-power nonvolatile memory device is fabricated by dispersing nickel oxide nanorods (nNiO) into a ferroelectric liquid crystal (FLC) host. The dipolar nNiO adsorbed ions in the FLC and thereby reduced the screening effect, which resulted in the enhanced memory behavior.

Charge Storage Characteristics of Si-Rich Silicon Nitride and the Effect of Tunneling Thickness on Nonvolatile Memory Performance

2011 ◽  
Vol 181-182 ◽  
pp. 307-311
Author(s):  
Hong Hanh Nguyen ◽  
Ngoc Son Dang ◽  
Van Duy Nguyen ◽  
Kyungsoo Jang ◽  
Kyunghyun Baek ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Nonvolatile Memory ◽  
Memory Performance ◽  
Charge Trapping ◽  
Oxide Thickness ◽  
Memory Window ◽  
Charge Storage ◽  
Operating Voltage ◽  
Silicon Clusters ◽  
Retention Characteristics

Nonvolatile memory (NVM) devices with nitride-nitride-oxynitride (NNO) stack structure using Si-rich silicon nitride (SiNx) as charge trapping layer on glass substrate were fabricated. Amorphous silicon clusters existing in the Si-rich SiNxlayer enhance the charge storage capacity of the devices. Low temperature poly-silicon (LTPS) technology, plasma-assisted oxidation/nitridation method to form a uniform ultra-thin tunneling layer, and an optimal Si-rich SiNxcharge trapping layer were used to fabricate NNO NVM devices with different tunneling thickness 2.3, 2.6 and 2.9 nm. The increase memory window, lower voltage operation but little scarifying in retention characteristics of nitride trap NVM devices had been accomplished by reducing the tunnel oxide thickness. The fabricated NVM devices with 2.9 nm tunneling thickness shows excellent electrical properties, such as a low threshold voltage, a high ON/OFF current ratio, a low operating voltage of less than ±9 V and a large memory window of 2.7 V, which remained greater than 72% over a period of 10 years.

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