Impact of HfTaO Buffer Layer on Data Retention Characteristics of Ferroelectric-Gate FET for Nonvolatile Memory Applications

2011 ◽  
Vol 58 (2) ◽  
pp. 370-375 ◽  
Author(s):  
Minghua Tang ◽  
Xiaolei Xu ◽  
Zhi Ye ◽  
Yoshihiro Sugiyama ◽  
Hiroshi Ishiwara
Keyword(s):  
Buffer Layer ◽  
Nonvolatile Memory ◽  
Data Retention ◽  
Retention Characteristics ◽  
Memory Applications

Charge storage and data retention characteristics of forming gas-annealed Gd2O3-nanocrystal nonvolatile memory cell

2012 ◽  
Vol 52 (8) ◽  
pp. 1627-1631 ◽  
Author(s):  
Jer-Chyi Wang ◽  
Chih-Ting Lin ◽  
Chi-Hsien Huang ◽  
Chao-Sung Lai ◽  
Chin-Hsiang Liao
Keyword(s):  
Nonvolatile Memory ◽  
Memory Cell ◽  
Charge Storage ◽  
Data Retention ◽  
Retention Characteristics

Lead Barium Zirconate Ferroelectric Films with ZrO[sub 2] Buffer Layer for Nonvolatile Memory Applications

2006 ◽  
Vol 9 (7) ◽  
pp. F57 ◽  
Author(s):  
Hung-Yao Chen ◽  
Jen-Po Lin ◽  
Jenn-Ming Wu ◽  
Hsin-Erh Huang ◽  
Hui-Yun Bor
Keyword(s):  
Buffer Layer ◽  
Nonvolatile Memory ◽  
Barium Zirconate ◽  
Ferroelectric Films ◽  
Memory Applications

scholarly journals High Pressure Deuterium Passivation of Charge Trapping Layer for Nonvolatile Memory Applications

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1316
Author(s):  
Jae-Young Sung ◽  
Jun-Kyo Jeong ◽  
Woon-San Ko ◽  
Jun-Ho Byun ◽  
Hi-Deok Lee ◽  
...  
Keyword(s):  
High Pressure ◽  
Nonvolatile Memory ◽  
Charge Trapping ◽  
Memory Device ◽  
Trap Density ◽  
Flat Band ◽  
Data Retention ◽  
Retention Model ◽  
A Charge ◽  
Memory Applications

In this study, the deuterium passivation effect of silicon nitride (Si3N4) on data retention characteristics is investigated in a Metal-Nitride-Oxide-Silicon (MNOS) memory device. To focus on trap passivation in Si3N4 as a charge trapping layer, deuterium (D2) high pressure annealing (HPA) was applied after Si3N4 deposition. Flat band voltage shifts (ΔVFB) in data retention mode were compared by CV measurement after D2 HPA, which shows that the memory window decreases but charge loss in retention mode after program is suppressed. Trap energy distribution based on thermal activated retention model is extracted to compare the trap density of Si3N4. D2 HPA reduces the amount of trap densities in the band gap range of 1.06–1.18 eV. SIMS profiles are used to analyze the D2 profile in Si3N4. The results show that deuterium diffuses into the Si3N4 and exists up to the Si3N4-SiO2 interface region during post-annealing process, which seems to lower the trap density and improve the memory reliability.

Impact of oxygen incorporation at the Si3N4∕Al2O3 interface on retention characteristics for nonvolatile memory applications

2008 ◽  
Vol 93 (2) ◽  
pp. 022101 ◽  
Author(s):  
Man Chang ◽  
Yongkyu Ju ◽  
Joonmyoung Lee ◽  
Seungjae Jung ◽  
Hyejung Choi ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
Oxygen Incorporation ◽  
Retention Characteristics ◽  
Memory Applications

•• Recent Progress in Ferroelectic-gate FETs

2002 ◽  
Vol 748 ◽  
Author(s):  
Hiroshi Ishiwara ◽  
Byung-Eun Park
Keyword(s):  
Buffer Layer ◽  
Recent Progress ◽  
Ferroelectric Film ◽  
Experimental Results ◽  
Buffer Layers ◽  
Data Retention ◽  
High K ◽  
Retention Characteristics ◽  
High K Dielectric ◽  
Low Capacitance

ABSTRACTRecent progress in the research of ferroelectric-gate FETs is reviewed mainly from a view-point of the data retention characteristics. First, importance of insulator-inserted gate structures such as an MFIS (M; metal, F; ferroelectric, I; insulator, S; semiconductor) or MFMIS structure is described and the necessary conditions for the insulating buffer layer and the ferroelectric film are discussed. Then, experimental results for the SiO2 and high-k dielectric buffer layers combined with such ferroelectric films as SBT (SrBi2Ta2O9) and BLT ((Bi,La)4Ti3O12) are presented, in which particular attention is paid to the discussion on the induced charge matching between the buffer layer and the ferroelectric film. As an example, it is shown in a Pt/BLT/LaAlO3/Si diode that the high and low capacitance values written by positive and negative pulses can be retained at least for 3 days. Finally, recent experimental results on the data retention characteristics of the ferroelectric-gate FETs are presented.

scholarly journals High-performance Ni/Yb2O3/TaN Programmable Memory Cell for Nonvolatile Memory Applications

2012 ◽  
pp. 74-77
Author(s):  
Somnath Mondal ◽  
Fa-Hsyang Chen ◽  
Tung-Ming Pan
Keyword(s):  
Resistive Switching ◽  
Nonvolatile Memory ◽  
High Performance ◽  
Sandwich Structure ◽  
Oxygen Vacancies ◽  
Memory Cell ◽  
Switching Behavior ◽  
Electrical Performance ◽  
Data Retention ◽  
Memory Applications

Resistive switching in Ni/Yb2O3/TaN programmable memory cells was investigated. We proposed a rearrangement of oxygen vacancies under electric field plays role in resistive switching. Under negative bias, oxygen vacancies or other metallic defects migrate through Yb2O3 oxide and SET occurs. A reproducible resistance switching behavior was observed with high resistance ratio of about 105 with excellent data retention, and good immunity to read disturbance, are also revealed. In particular, the simple sandwich structure and excellent electrical performance of the memory cell making them ideal for the basis for highspeed, high-density, nonvolatile memory applications.

‥Recent Progress in Ferroelectic-gate FETs

2002 ◽  
Vol 747 ◽  
Author(s):  
Hiroshi Ishiwara ◽  
Byung-Eun Park
Keyword(s):  
Buffer Layer ◽  
Recent Progress ◽  
Ferroelectric Film ◽  
Experimental Results ◽  
Buffer Layers ◽  
Data Retention ◽  
High K ◽  
Retention Characteristics ◽  
High K Dielectric ◽  
Low Capacitance

ABSTRACTRecent progress in the research of ferroelectric-gate FETs is reviewed mainly from a view-point of the data retention characteristics. First, importance of insulator-inserted gate structures such as an MFIS (M; metal, F; ferroelectric, I; insulator, S; semiconductor) or MFMIS structure is described and the necessary conditions for the insulating buffer layer and the ferroelectric film are discussed. Then, experimental results for the SiO2 and high-k dielectric buffer layers combined with such ferroelectric films as SBT (SrBi2Ta 2O9) and BLT ((Bi,La)4Ti3O12) are presented, in which particular attention is paid to the discussion on the induced charge matching between the buffer layer and the ferroelectric film. As an example, it is shown in a Pt/BLT/LaAlO3/Si diode that the high and low capacitance values written by positive and negative pulses can be retained at least for 3 days. Finally, recent experimental results on the data retention characteristics of the ferroelectric-gate FETs are presented.

scholarly journals Charge-Trapping Devices Using Multilayered Dielectrics for Nonvolatile Memory Applications

2013 ◽  
Vol 2013 ◽  
pp. 1-5
Author(s):  
Wen-Chieh Shih ◽  
Chih-Hao Cheng ◽  
Joseph Ya-min Lee ◽  
Fu-Chien Chiu
Keyword(s):  
Nonvolatile Memory ◽  
Field Effect Transistors ◽  
Charge Trapping ◽  
Memory Window ◽  
Electrical Characteristics ◽  
Data Retention ◽  
Device Structure ◽  
Threshold Voltage Shift ◽  
Memory Applications ◽  
Trapping Devices

Charge-trapping devices using multilayered dielectrics were studied for nonvolatile memory applications. The device structure is Al/Y2O3/Ta2O5/SiO2/Si (MYTOS). The MYTOS field effect transistors were fabricated using Ta2O5as the charge storage layer and Y2O3as the blocking layer. The electrical characteristics of memory window, program/erase characteristics, and data retention were examined. The memory window is about 1.6 V. Using a pulse voltage of 6 V, a threshold voltage shift of ~1 V can be achieved within 10 ns. The MYTOS transistors can retain a memory window of 0.81 V for 10 years.

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