450 mm Silicon Wafers Challenges - Wafer Thickness Scaling

2019 ◽  
Vol 16 (6) ◽  
pp. 3-13 ◽  
Author(s):  
Michael Goldstein ◽  
Masaharu Watanabe
Keyword(s):  
Silicon Wafers ◽  
Wafer Thickness

scholarly journals Backside Chippings Improvement through Wafer Dicing Parameter Optimization and Understanding the Anistropic Silicon Properties

2021 ◽  
pp. 144-152
Author(s):  
Aiza Marie E. Agudon ◽  
Bryan Christian S. Bacquian
Keyword(s):  
Integrated Circuit ◽  
Electronic Devices ◽  
Silicon Wafers ◽  
Form Complex ◽  
Work Related ◽  
Front End ◽  
Wafer Thickness ◽  
Fully Automatic ◽  
Direct Materials ◽  
Selection Of

Semiconductor Companies and Industries soar high as the trend for electronic gadgets and devices increases. Transition from “manual” to “fully automatic” application is one of the advantages why consumer adapt to changes and prefer electronic devices as one of daily answers. Individuals who admire these electronic devices often ask how they are made. As we look inside each device, we can notice interconnected microchips commonly called IC (Integrated Circuit). These are specially prepared silicon wafers where integrated circuit are developed. Commonly, each device is composed of numerous microchips depending on the design and functionality IC production is processed from “front-end” to “back-end” assembly. Front-end assembly includes wafer fabrication where electrical circuitry is prepared and integrated to every single silicon wafers. Back-end assembly covers processing the wafer by cutting into smaller individual and independent components called “dice”. Each dice will be placed into Leadframe, bonded with wires prior encapsulating with mold compounds. After molding, each IC will be cut through a process called singulation. Afterwards, all molded units are subjected for functional testing. Dice is central to each IC; it is where miniature transistor, resistor and capacitor are integrated to form complex small circuitry in microchips. Pre-assembly (Pre-assy) stations have the first hand prior to all succeeding stations. Live wafers are primary direct materials processed in these stations. Robust work instruction and parameter must be practiced during handling and processing to avoid gross rejection and possible work-related defects. The paper is all about the challenges to resolve and improved the backside chippings in 280um wafer thickness in mechanical dicing saw. The conventional Mechanical dicing process induce a lot of mechanical stress and vibration during the cutting process which oftentimes lead to backside chipping and die crack issues. However, backside chippings can mitigate with proper selection of parameter settings and understand the silicon wafer properties.

Laser Ultrasonic Instrumentation for Accurate Temperature Measurement of Silicon Wafers in Rapid Thermal Processing Systems

1998 ◽  
Vol 525 ◽  
Author(s):  
Dan Klimek ◽  
Brian Anthonyt ◽  
Agostino Abbate ◽  
Petros Kotidis
Keyword(s):  
Temperature Measurement ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Silicon Wafers ◽  
Thickness Variation ◽  
Laser Ultrasonic ◽  
Ultrasonic Methods ◽  
Wafer Thickness ◽  
Accurate Temperature ◽  
Accurate Temperature Measurement

ABSTRACTResults are presented that demonstrate the use of laser ultrasonic methods to determine the temperature of silicon wafers under conditions consistent with applications in the RTP industry. The results show that it is possible to measure the temperature of Si(100) wafers to an accuracy approaching ± 1°C (1σ) even with wafer thickness variation over a range of 2 to 3 percent.

A Systematic Approach to Thinning Silicon Wafers to the sub-40μm Thickness Range

2006 ◽  
Vol 3 (2) ◽  
pp. 86-94 ◽  
Author(s):  
Parthiban Arunasalam ◽  
Matthew H. Gordon ◽  
Leonard W. Schaper
Keyword(s):  
Systematic Approach ◽  
Silicon Wafers ◽  
Mechanical Polishing ◽  
Thickness Variation ◽  
Wafer Thickness ◽  
Chemical Etch ◽  
Custom Made ◽  
Carrier Wafer ◽  
Total Thickness Variation ◽  
Wafer Thinning

The present trend in electronics packaging is the stacking of die at the wafer or chip level. However to ensure stacked chip packages maintain overall low height and weight package profile, silicon wafers have to undergo extensive wafer thinning processes. In this work, a systematic approach to thinning silicon wafers down to sub-40μm in thickness is presented. This paper will cover a detailed three stage wafer thinning method, which includes the mechanical back-lapping method for the bulk removal process and a combination of mechanical polishing and spin-spray wet chemical etch method for the fine removal wafer thinning process. The results will show that by just utilizing the mechanical back-lapping and mechanical polishing process the wafers can be easily thinned from 380μm to less than 50μm with ±2.5μm Total Thickness Variation (TTV). These back-lapped wafers are then further thinned by the spin-spray etching method to achieve final wafer thickness of less than 40μm. The paper will also show that by utilizing a modified carrier wafer, the handling of these sub-40μm ultra-thin wafers do not require custom made tools and can be easily integrated into existing wafer handling tools.

Arsenic segregation in polysilicon

1983 ◽  
Vol 41 ◽  
pp. 154-155 ◽  
Author(s):  
P.E. Batson ◽  
C.R.M. Grovenor ◽  
D.A. Smith ◽  
C. Wong
Keyword(s):  
Incident Beam ◽  
Silicon Wafers ◽  
Chemical Polishing ◽  
Bright Field Image ◽  
Beam Size ◽  
Stem Analysis ◽  
Bright Field ◽  
Twin Boundaries ◽  
X Ray ◽  
Line Scan

In this work As doped polysilicon was deposited onto (100) silicon wafers by APCVD at 660°C from a silane-arsine mixture, followed by a ten minute anneal at 1000°C, and in one case a further ten minute anneal at 700°C. Specimens for TEM and STEM analysis were prepared by chemical polishing. The microstructure, which is unchanged by the final 700°C anneal,is shown in Figure 1. It consists of numerous randomly oriented grains many of which contain twins.X-ray analysis was carried out in a VG HB5 STEM. As K α x-ray counts were collected from STEM scans across grain and twin boundaries, Figures 2-4. The incident beam size was about 1.5nm in diameter, and each of the 20 channels in the plots was sampled from a 1.6nm length of the approximately 30nm line scan across the boundary. The bright field image profile along the scanned line was monitored during the analysis to allow correlation between the image and the x-ray signal.

Preparation of integrated circuits for TEM electromigration in situ studies

1986 ◽  
Vol 44 ◽  
pp. 882-883
Author(s):  
J. V. Maskowitz ◽  
W. E. Rhoden ◽  
D. R. Kitchen ◽  
R. E. Omlor ◽  
P. F. Lloyd
Keyword(s):  
Integrated Circuits ◽  
Crystallographic Orientation ◽  
Silicon Wafers ◽  
Minimum Size ◽  
Test Vehicle ◽  
In Situ Studies ◽  
Boron Doped ◽  
Doped Silicon ◽  
Drill Holes

The fabrication of the aluminum bridge test vehicle for use in the crystallographic studies of electromigration involves several photolithographic processes, some common, while others quite unique. It is most important to start with a clean wafer of known orientation. The wafers used are 7 mil thick boron doped silicon. The diameter of the wafer is 1.5 inches with a resistivity of 10-20 ohm-cm. The crystallographic orientation is (111).Initial attempts were made to both drill and laser holes in the silicon wafers then back fill with photoresist or mounting wax. A diamond tipped dentist burr was used to successfully drill holes in the wafer. This proved unacceptable in that the perimeter of the hole was cracked and chipped. Additionally, the minimum size hole realizable was > 300 μm. The drilled holes could not be arrayed on the wafer to any extent because the wafer would not stand up to the stress of multiple drilling.

Low temperature drive-in of surface-deposited copper in silicon wafers

2004 ◽  
Vol 27 (1-3) ◽  
pp. 435-438 ◽  
Author(s):  
M. L. Polignano ◽  
D. Caputo ◽  
C. Carpanese ◽  
G. Salvà ◽  
L. Vanzetti
Keyword(s):  
Low Temperature ◽  
Silicon Wafers

Recombination Characteristics of Single-Crystalline Silicon Wafers with a Damaged Near-Surface Layer

2013 ◽  
Vol 58 (2) ◽  
pp. 142-150 ◽  
Author(s):  
A.V. Sachenko ◽  
◽  
V.P. Kostylev ◽  
V.G. Litovchenko ◽  
V.G. Popov ◽  
...  
Keyword(s):  
Surface Layer ◽  
Crystalline Silicon ◽  
Silicon Wafers ◽  
Single Crystalline Silicon ◽  
Near Surface ◽  
Single Crystalline
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