Laser Spike Annealing of Strained Si/ Strained Si0.3Ge0.7/ Relaxed Si0.7Ge0.3 Dual Channel High Mobility p-MOSFETs

2019 ◽  
Vol 3 (2) ◽  
pp. 355-362
Author(s):  
Cait Ni Chleirigh ◽  
Xiaoru Wang ◽  
Gana Rimple ◽  
Yun Wang ◽  
Michael Canonico ◽  
...  
Keyword(s):  
High Mobility ◽  
Strained Si ◽  
Dual Channel ◽  
Spike Annealing

Channel Engineering of SiGe-Based Heterostructures for High Mobility MOSFETs

2001 ◽  
Vol 686 ◽  
Author(s):  
Christopher W. Leitz ◽  
Matthew T. Currie ◽  
Minjoo L. Lee ◽  
Zhi-Yuan Cheng ◽  
Dimitri. A. Antoniadis ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
High Mobility ◽  
Hole Mobility ◽  
Oxide Semiconductor ◽  
Strained Si ◽  
Alloy Scattering ◽  
Dual Channel ◽  
Significant Performance ◽  
Performance Gains ◽  
Long Channel

AbstractStrained Si- and SiGe-based heterostructure metal-oxide-semiconductor field-effect transistors (MOSFETs) grown on relaxed SiGe virtual substrates exhibit dramatic electron and hole mobility enhancements over bulk Si, making them promising candidates for next generation complementary MOSFET (CMOS) devices. The most heavily investigated heterostructures consist of single strained Si layers grown upon relaxed SiGe substrates. While this configuration offers significant performance gains for both n- and p-MOSFETs, the enhanced hole mobility remains much lower than the enhanced electron mobility. By contrast, a combination of buried compressively strained Si1−yGey layers and tensile strained Si surface layers grown on relaxed Si1−xGex (x < y), hereafter referred to as dual channel heterostructures, offers nearly symmetric electron and hole mobilities without compromising n-MOSFET device performance. To investigate these heterostructures, we study the effects of alloy scattering on channel mobility in long channel MOSFETs. By using the combination of a buried Si0.2Ge0.8 channel and a strained Si surface channel grown on a relaxed Si0.5Ge0.5 virtual substrate, we have achieved nearly symmetric electron and hole mobility in the same heterostructure. By employing different virtual substrate compositions, we can decouple the effects of strain and alloy scattering in both tensile strained surface channels and compressively strained buried channels. We show that significant hole mobility enhancements can be achieved in dual channel heterostructures, even for buried channel compositions where alloy scattering is expected to be most severe. Furthermore, we show that alloy scattering in tensile strained SiGe surface channels impacts electrons much more severely than holes. Taken together, these results demonstrate that dual channel heterostructures can offer symmetric carrier mobilities and provide excellent performance gains for CMOS applications.

Low temperature mobility improvement in high-mobility strained-Si/Si1-xGex multilayer MOSFETs

1998 ◽  
Vol 08 (PR3) ◽  
pp. Pr3-57-Pr3-60
Author(s):  
J. B. Roldán ◽  
F. Gámiz ◽  
J. A. López-Villanueva ◽  
J. E. Carceller
Keyword(s):  
Low Temperature ◽  
High Mobility ◽  
Strained Si

Nanoscale Heat Conduction in the SOI, Strained-Si and Tri-Gate Transistors

2004 ◽  
Author(s):  
Mehdi Asheghi
Keyword(s):  
Carrier Mobility ◽  
High Mobility ◽  
Silicon On Insulator ◽  
Strained Silicon ◽  
Device Performance ◽  
Strained Si ◽  
Insulator Layer ◽  
Junction Capacitance ◽  
Induced Changes ◽  
Soi Technology

There have been many attempts in the recent years to improve the device performance by enhancing carrier mobility by using the strained-induced changes in silicon electronic bands [1–4] or reducing the junction capacitance in silicon-on-insulator (SOI) technology. Strained silicon on insulator (SSOI) is another promising technology, which is expected to show even higher performance, in terms of speed and power consumption, comparing to the regular strained-Si transistors. In this technology, the strained silicon is incorporated in the silicon on insulator (SOI) technology such that the strained-Si introduces high mobility for electrons and holes and the insulator layer (usually SiO2) exhibits low junction capacitance due to its small dielectric constant [5, 6]. In these devices a layer of SiGe may exist between the strined-Si layer and insulator (strained Si-on-SiGe-on-insulator, SGOI) [6] or the strained-Si layer can be directly on top of the insulator [7]. Latter is advantageous for eliminating some of the key problems associated with the fabrication of SGOI.

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